參數(shù)資料
型號(hào)： GS4576S09L-25
廠商： GSI TECHNOLOGY
元件分類： DRAM
英文描述： DDR DRAM, PBGA144
封裝： UBGA-144
文件頁數(shù)： 42/64頁
文件大?。?/td> 2691K
代理商： GS4576S09L-25
Preliminary
GS4576S09/18L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 4/2011
47/64
2011, GSI Technology
Capacitance
Description
Symbol
Conditions
Min.
Max.
Unit
Address/control input capacitance
CI
TA = 25° C; f = 100 MHz
VDD = VDDQ = 1.8 V
1.0
2.0
pF
Input/Output capacitance
(D, Q, DM, and QK, QK)
CO
3.0
4.5
pF
Clock capacitance (CK/CK and DK/DK)
CCK
1.5
2.5
pF
JTAG pins
CJTAG
1.5
4.5
pF
Notes:
1. Capacitance is not tested on the ZQ pin.
2. JTAG Pins are tested at 50 MHz.
IDD Operating Conditions
Description
Condition
Symbol
-18
-24
-25
-33
Un
its
Standby Current
tCK = idle, All banks idle; No inputs
toggling.
ISB1 (VDD) x9/x18
TBD
mA
ISB1 (VEXT)
TBD
Active Standby Current
CS = 1, No commands; Bank address
incremented and half address/data change
once every four clock cycles.
ISB2 (VDD) x9/x18
TBD
mA
ISB2 (VEXT)
TBD
Operational Current
BL = 2, Sequential bank access; Bank
transitions once every tRC; Half address
transitions once every tRC; Read followed
by Write sequence; Continuous data during
Write Commands.
IDD1 (VDD) x9/x18
TBD
mA
IDD1 (VEXT)
TBD
Operational Current
BL = 4, Sequential bank access; Bank
transitions once every tRC; Half address
transitions once every tRC; Read followed
by Write sequence; Continuous data during
Write Commands.
IDD2 (VDD) x9/x18
TBD
mA
IDD2 (VEXT)
TBD
Operational Current
BL = 8, Sequential bank access; Bank
transitions once every tRC; Half address
transitions once every tRC. Read followed
by Write sequence; Continuous data during
Write Commands.
IDD3 (VDD) x9/x18
TBD
mA
IDD3 (VEXT)
TBD
Burst Refresh Current
Eight bank cyclic refresh; Continuous
address/data; Command bus remains in
refresh for all eight banks.
IREF1 (VDD) x9/x18
TBD
mA
IREF1 (VEXT)
TBD
Distributed Refresh Current
Single bank refresh; Sequential bank
access; Half address transitions once every
tRC; Continuous data.
IREF2 (VDD)x9/x18
TBD
mA
IREF2 (VEXT)
TBD
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