參數(shù)資料
型號： HY5R288HC
英文描述： -|2.5V|8K|40|Direct RDRAM - 288M
中文描述： - |為2.5V | 8K的| 40 |直接RDRAM的- 288M
文件頁數(shù)： 27/64頁
文件大?。?/td> 4542K
代理商： HY5R288HC
Rev.0.9 / Dec.2000
27
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
Control Register Packets
Table 13 summarizes the formats of the four packet types for
control register transactions. Table 14 summarizes the fields
that are used within the packets.
Figure 25: shows the transaction format for the SETR,
CLRR, and SETF commands. These transactions consist of a
single SRQ packet, rather than four packets like the SWR
and SRD commands. The same framing sequence on the
CMD input is used, however.
Figure 25: SETR, CLRR,SETF Transaction
SCK
CMD
SIO0
T
20
SRQ packet - SETR/CLRR/SETF
1111
00000000...00000000
SRQ packet - SETR/CLRR/SETF
0000
SIO1
T
4
The packet is repeated
from SIO0 to SIO1
1
1
1
1
0
0
0
0
Table 13: Control Register Packet Formats
SCK
Cycle
SIO0 or
SIO1
for SRQ
SIO0 or
SIO1
for SA
SIO0 or
SIO1
for SINT
SIO0 or
SIO1
for SD
SCK
Cycle
SIO0 or
SIO1
for SRQ
SIO0 or
SIO1
for SA
SIO0 or
SIO1
for SINT
SIO0 or
SIO1
for SD
0
rsrv
rsrv
0
SD15
8
SOP1
SA7
0
SD7
1
rsrv
rsrv
0
SD14
9
SOP0
SA6
0
SD6
2
rsrv
rsrv
0
SD13
10
SBC
SA5
0
SD5
3
rsrv
rsrv
0
SD12
11
SDEV4
SA4
0
SD4
4
rsrv
SA11
0
SD11
12
SDEV3
SA3
0
SD3
5
SDEV5
SA10
0
SD10
13
SDEV2
SA2
0
SD2
6
SOP3
SA9
0
SD9
14
SDEV1
SA1
0
SD1
7
SOP2
SA8
0
SD8
15
SDEV0
SA0
0
SD0
Table 14: Field Description for Control Register Packets
Field
Description
rsrv
Reserved. Should be driven as “0” by controller.
SOP3..SOP0
0000 - SRD. Serial read of control register {SA11..SA0} of RDRAM {SDEV5..SDEV0}.
0001 - SWR. Serial write of control register {SA11..SA0} of RDRAM {SDEV 5..SDEV0}.
0010 - SETR. Set Reset bit, all control registers assume their reset values.
a
Must be followed by a delay and a CLRR
b
0100 - SETF. Set fast (normal) clock mode. 4 t
SCYCLE
delay until CLRR command
1011 - CLRR. Clear Reset bit, all control registers retain their reset values.
a
4 t
SCYCLE
delay until next command.
1111 - NOP. No serial operation.
0011, 0101-1010, 1100-1110 - RSRV. Reserved encodings.
SDEV5..SDEV0
Serial device. Compared to SDEVID 5..SDEVID0 field of INIT control register field to select the RDRAM to which the trans-
action is directed.
SBC
Serial broadcast. When set, RDRAMs ignore {SDEV 5..SDEV0} for RDRAM selection.
SA11..SA0
Serial address. Selects which control register of the selected RDRAM is read or written.
SD15..SD0
Serial data. The 16 bits of data written to or read from the selected control register of the selected RDRAM.
a. The SETR and CLRR commands must always be applied in two successive transactions to RDRAMs; i.e. they may not be used in isolation. This is called “ SETR/CLRR Reset ”.b. A minimum gap
equal to the larger of {16 * t
SCYCLE
, 2816 * t
CYCLE
} must be inserted between a SETR / CLRR command pair.
相關(guān)PDF資料
PDF描述
HY5V16CF 1Mx16|3.3V|4K|H|SDR SDRAM - 16M
HY5V16CF-H x16 SDRAM
HY5V16CF-S x16 SDRAM
HY6116-10 x8 SRAM
HY6116-12 x8 SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HY5S2B6DLF-BE 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM
HY5S2B6DLFP-BE 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM
HY5S2B6DLFP-SE 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM
HY5S2B6DLF-SE 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM
HY5S5B2BLF-6E 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M (8Mx32bit) Mobile SDRAM
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*