參數(shù)資料
型號： HY5R288HC
英文描述： -|2.5V|8K|40|Direct RDRAM - 288M
中文描述： - |為2.5V | 8K的| 40 |直接RDRAM的- 288M
文件頁數(shù)： 44/64頁
文件大小： 4542K
代理商： HY5R288HC
44
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
Rev. 0.9 / Dec.2000
Current and Temperature Control
Figure 52: shows an example of a transaction which
performs current control calibration. It is necessary to
perform this operation once to every RDRAM in every
t
CCTRL
interval in order to keep the I
OL
output current in its
proper range.
This example uses four COLX packets with a CAL
command. These cause the RDRAM to drive four calibration
packets Q(a0) a time t
CAC
later. An offset of t
RDTOCC
must
be placed between the Q(a0) packet and read data Q(a1)from
the same device. These calibration packets are driven on the
DQA4..3 and DQB4..3 wires. The TSQ bit of the INIT
register is driven on the DQA5 wire during same interval as
the calibration packets. The remaining DQA and DQB wires
are not used during these calibration packets. The last COLX
packet also contains a SAM command (concatenated with
the CAL command). The RDRAM samples the last calibra-
tion packet and adjusts its I
OL
current value.
Unlike REF commands, CAL and SAM commands cannot
be broadcast. This is because the calibration packets from
different devices would interfere. Therefore, a current
control transaction must be sent every t
CCTRL
/N, where N is
the number of RDRAMs on the Channel. The device field
Da of the address a0 in the CAL/SAM command should be
incremented after each transactions.
Figure53 shows an example of a temperature calibration
sequence to the RDRAM. This sequence is broadcast once
every t
TEMP
interval to all the RDRAMs on the Channel.
The TCEN and TCAL are ROP commands, and cause the
slew rate of the output drivers to adjust for temperature drift.
During the quiet interval t
TCQUIET
the devices being cali-
brated can’t be read, but they can be written.
Figure 52: Current Control CAL/SAM Transaction Example
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
24
T
28
T
17
T
21
T
25
T
29
T
18
T
22
T
26
T
30
T
19
T
23
T
27
T
31
T
32
T
36
T
40
T
44
T
33
T
37
T
41
T
45
T
34
T
38
T
42
T
46
T
35
T
39
T
43
T
47
Transaction a0: CAL/SAM
Transaction a1: RD
Transaction a2: CAL/SAM
a0 = {Da, Bx}
a1 = {Da, Bx}
a2 = {Da+1, Bx}
CAL a0
CAL a2
Q (a0)
t
CAC
CAL a0
CAL a0
CAL/SAM a0
CAL
DQA5 of the first calibrate packet has the inverted TSQ bit
of INIT control register; i.e. logic 0 or high voltage means hot temp.
when used for monitoring, it should be enabled with the
the DQA3bit ()current control one value) in case there is no RDRAM present;
Q (a1)
t
READTOCC
Read data from the same
device from an earlier RD
command must be at this
packet position or earlier.
Read data from a different
device from an earlier RD
command can be anywhere
prior to the Q(a0) packet. .
Q (a1)
t
CCSAMTOREAD
Read data from a different
device from a later RD
command can be anywhere
after to the Q(a0) packet.
Read data from the same device
from a later RD command must
be at this packet position or
later.
t
CCTRL
HotTemp = DQA5 * DQA3
Note that DQB3 could be used instead of DQA3
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