參數(shù)資料
型號(hào): HY5R288HC
英文描述: -|2.5V|8K|40|Direct RDRAM - 288M
中文描述: - |為2.5V | 8K的| 40 |直接RDRAM的- 288M
文件頁數(shù): 43/64頁
文件大?。?/td> 4542K
代理商: HY5R288HC
Rev.0.9 / Dec.2000
43
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
Figure 50: REFA/REFP Refresh Transaction
Example
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
24
T
28
T
17
T
21
T
25
T
29
T
18
T
22
T
26
T
30
T
19
T
23
T
27
T
31
T
32
T
36
T
40
T
44
T
33
T
37
T
41
T
45
T
34
T
38
T
42
T
46
T
35
T
39
T
43
T
47
REFA a0
ACT c0
t
RAS
t
RC
t
RP
Transaction a: REFA
Transaction b: xx
a0 = {Broadcast,Ba,REFR}
b0 = {Db, /={Ba,Ba+1,Ba-1}, Rb}
a1 = {Broadcast,Ba}
Transaction c: xx
Transaction d: REFA
c0 = {Dc, ==Ba, Rc}
d0 = {Broadcast,Ba+1,REFR}
REFA d0
t
REF
/2
BBIT+RBIT
BBIT = # bank address bits
RBIT = # row address bits
REFB = REFB3..REFB0
REFR = REFR8..REFR0
ACT b0
t
RR
REFP a1
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
24
T
28
T
17
T
21
T
25
T
29
T
18
T
22
T
26
T
30
T
19
T
23
T
27
T
31
T
32
T
36
T
40
T
44
T
33
T
37
T
41
T
45
T
34
T
38
T
42
T
46
T
35
T
39
T
43
T
47
ROP
DQS=0
b,c
SCK
CMD
SIO0
SIO1
0
1
0/1
a
0/1
a
DQS=1
b
t
CE
a
Use 0 for NAP exit, 1 for PDN exit
The packet is repeated
from SIO0 to SIO1
restricted
Power
State
DQS=0
DQS=1
t
S4
t
H4
restricted
STBY
NAP/PDN
(
NAPX)t
SCYCLE
)/(
256PDNXt
SCYCLE
)
t
S4
t
H4
COP
XOP
ROP
COP
XOP
REFA b12
REFA b31
t
BURST
32 bank refresh sequence
Figure 51: NAP/PDN Exit -t
BURST
Requirement
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