參數(shù)資料
型號(hào)： HY5R288HC
英文描述： -|2.5V|8K|40|Direct RDRAM - 288M
中文描述： - |為2.5V | 8K的| 40 |直接RDRAM的- 288M
文件頁(yè)數(shù)： 55/64頁(yè)
文件大?。?/td> 4542K
代理商： HY5R288HC
Rev.0.9 / Dec.2000
55
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
The SCK clock is also used for sampling data on RSL inputs
in one situation. Figure 48: shows the PDN and NAP exit
sequences. If the PSX field of the INIT register is zero (see
Figure 27:), then the PDN and NAP exit sequences are
broadcast; i.e. all RDRAMs that are in PDN or NAP will
perform the exit sequence. If the PSX field of the INIT
register is one, then the PDN and NAP exit sequences are
directed; i.e. only one RDRAM that is in PDN or NAP will
perform the exit sequence.
The address of that RDRAM is specified on the DQA[5:0]
bus in the set hold window t
S3
/t
H3
arouond the rising edge of
SCK. This is shown in Figure 58:. The SCK timing point is
measured at the 50% level, and the DQA[5:0] bus signals are
measured at the V
REF
level.
Figure 58: CMOS Timing - Device Address for NAP or PDN Exit
V
IH,CMOS
50%
V
IL,CMOS
80%
20%
SCK
V
DIH
V
REF
V
DIL
80%
20%
DQA[5:0]
t
S3
t
H3
PDEV
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