參數(shù)資料
型號(hào)： HY5R288HC
英文描述： -|2.5V|8K|40|Direct RDRAM - 288M
中文描述： - |為2.5V | 8K的| 40 |直接RDRAM的- 288M
文件頁(yè)數(shù)： 32/64頁(yè)
文件大?。?/td> 4542K
代理商： HY5R288HC
32
Rev.0.9/Dec.2000
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
. .
Figure 27: INIT Register
Figure 28: CNFGA Register
15 14 13 12 11 10
SDE
5
9
8
7
6
5
4
3
2
1
0
Control Register: INIT
Read/write register.
Reset values are undefined except as affected by SIO Reset as noted
below. SETR/CLRR Reset does not affect this register.
SDEVID5..0 - Serial Device Identification. Compared to SDEV5..0
serial address field of serial request packet for register read/write transac-
tions. This determines which RDRAM is selected for the register read or
write operation.
SDEVID resets to 3f
16
.
SDEVID4..SDEVID0
0
SRP PSX
NSR
PSR
LSR
0
PSX - Power Exit Select. PDN and NAP are exited with (=0) or without (=1) a device address on the
DQA5..0 pins.
SRP - SIO Repeater. Controls value on SIO1; SIO1=SIO0 if SRP=1, SIO1=1 if SRP=0.
SRP resets
to 1.
NAP Self-Refresh. NSR=1 enables self-refresh in NAP mode.
NSR resets to 0.
PDN Self-Refresh. PSR=1 enables self-refresh in PDN mode.
PSR resets to 0.
Low Power Self-Refresh. LSR=1 enables longer self-refresh interval. The self-refresh supply
current is reduced.
LSR resets to 0.
Temperature Sensing Enable. TEN=1 enables temperature sensing circuitry, permitting the TSQ bit
to be read to determine if a thermal trip point has been exceeded.
TEN resets to 0.
Temperature Sensing Output. TSQ=1 when a temperature trip point has been exceeded, TSQ=0
when it has not. TSQ is available during a current control operation (see Figure 52:).
RDRAM Disable. DIS=1 causes RDRAM to ignore NAP/PDN exit sequence, DIS=0 permits
normal operation. This mechanism disables an RDRAM.
DIS resets to 0.
Address: 021
16
TEN
TSQ
DIS
15 14 13 12 11 10
PVER5..0
= 000001
9
8
7
6
5
4
3
2
REFBIT2..0
= 101
1
0
Control Register: CNFGA
Address: 023
16
0
0
0
0
0
0
0
0
1
0
0
Read-only register.
REFBIT2..0 - Refresh Bank Bits. Specifies the number of
high order bank address bits to be ignored during REFA
and REFP commands. Permits multi-bank refresh in future
RDRAMs.
DBL - Doubled-Bank. DBL=1 means the device uses a
doubled-bank architecture with adjacent-bank dependency.
DBL=0 means no dependency.
MVER5..0 - Manufacturer Version. Specifies the manufac-
turer identification number.
PVER5..0 - Protocol Version. Specifies the Direct Protocol
version used by this device:
0 - Compliant with version 0.62 and ECO1-ECO18.
1 - Compliant with version 0.7 and ECO1-ECO38.
2 to 63 - Reserved
DBL
MVER5..0
= mmmmmm
Note : In RDRAMs with protocol version 1 PVER[5:0] = 000001,
the range of the PDNX field (PDNX[2:0] in the PDNX register)
may not be large enough to specify the location of the restricted
interval in Figure 47:. In this case, the effective t
S4
parameter
must increase and no row or column packets may overlap the
restricted interval. See Figure 47: and Table 17:.
相關(guān)PDF資料
PDF描述
HY5V16CF 1Mx16|3.3V|4K|H|SDR SDRAM - 16M
HY5V16CF-H x16 SDRAM
HY5V16CF-S x16 SDRAM
HY6116-10 x8 SRAM
HY6116-12 x8 SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HY5S2B6DLF-BE 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM
HY5S2B6DLFP-BE 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM
HY5S2B6DLFP-SE 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM
HY5S2B6DLF-SE 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM
HY5S5B2BLF-6E 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M (8Mx32bit) Mobile SDRAM
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*