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參數(shù)資料
| 型號： | HY5R288HC |
| 英文描述： | -|2.5V|8K|40|Direct RDRAM - 288M |
| 中文描述： | - |為2.5V | 8K的| 40 |直接RDRAM的- 288M |
| 文件頁數(shù)： | 51/64頁 |
| 文件大?。?/td> | 4542K |
| 代理商： | HY5R288HC |
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Rev.0.9 / Dec.2000
51
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
RSL - Clocking
Figure 54: is a timing diagram which shows the detailed
requirements for the RSL clock signals on the Channel.
The CTM and CTMN are differential clock inputs used for
transmitting information on the DQA and DQB, outputs.
Most timing is measured relative to the points where they
cross. The t
CYCLE
parameter is measured from the falling
CTM edge to the falling CTM edge. The t
CL
and t
CH
param-
eters are measured from falling to rising and rising to falling
edges of CTM. The t
CR
and t
CF
rise- and fall-time parame-
ters are measured at the 20% and 80% points.
The CFM and CFMN are differential clock outputs used for
receiving information on the DQA, DQB, ROW and COL
outputs. Most timing is measured relative to the points
where they cross. The t
CYCLE
parameter is measured from
the falling CFM edge to the falling CFM edge. The t
CL
and
t
CH
parameters are measured from falling to rising and rising
to falling edges of CFM. The t
CR
and t
CF
rise- and fall-time
parameters are measured at the 20% and 80% points.
The t
TR
parameter specifies the phase difference that may be
tolerated with respect to the CTM and CFM differential
clock inputs (the CTM pair is always earlier).
Figure 54: RSL Timing - Clock Signals
V
CIH
50%
V
CIL
80%
20%
CTM
CTMN
V
CIH
50%
V
CIL
80%
20%
CFM
CFMN
t
TR
t
CF
t
CF
t
CR
t
CR
t
CYCLE
t
CL
t
CH
t
CF
t
CF
t
CR
t
CR
t
CYCLE
t
CL
t
CH
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