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參數(shù)資料
| 型號： | HY5R288HC |
| 英文描述： | -|2.5V|8K|40|Direct RDRAM - 288M |
| 中文描述： | - |為2.5V | 8K的| 40 |直接RDRAM的- 288M |
| 文件頁數(shù)： | 33/64頁 |
| 文件大小： | 4542K |
| 代理商： | HY5R288HC |
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Rev.0.9 / Dec.2000
33
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
. .
Read-only register.
Figure 29: CNFGB Register
15 14 13 12 11 10
SVER5..0
= ssssss
9
8
CORG4..0
= 01000
7
6
5
4
3
DEVTYP2..0
= 000
2
1
0
Control Register: CNFGB
Address: 024
16
0
0
0
0
0
0
0
0
1
0
B
BYT - Byte width. B=1 means the device reads and
writes 9-bit memory bytes. B=0 means 8 bits.
DEVTYP2..0 - Device type. DEVTYP = 000 means
that this device is an RDRAM.
BYT
SPT
SPT - Split-core. SPT=1 means the core is split, SPT=0 means it is not.
CORG4..0 - Core organization. This field specifies the number of bank (5
bits), row (9bits), and column (7 bits) address bits.
SVER5..0 - Stepping version. Specifies the mask version number of this
device.
Figure 30: TEST Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Read/write register.
Reset value of TEST34 is zero (from SIO Reset)
This register are used for testing purposes. It must not
be read or written after SIO Reset except prior to the
SETR/CLRR sequence when it is written with a
temporary value. After SETR/CLRR it is rewritten to
0000
16
.
Control Register: TEST34
Address: 022
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 31: DEVID Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Read/write register.
Reset value is undefined.
Device Identification register.
DEVID4..DEVID0 is compared to DR4..DR0,
DC4..DC0, and DX4..DX0 fields for all memory read
or write transactions. This determines which RDRAM
is selected for the memory read or write transaction.
Control Register: DEVID
Address: 040
16
0
DEVID4..DEVID0
0
0
0
0
0
0
0
0
0
0
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相關代理商/技術參數(shù) |
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