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參數(shù)資料
| 型號(hào)： | HY5R288HC |
| 英文描述： | -|2.5V|8K|40|Direct RDRAM - 288M |
| 中文描述： | - |為2.5V | 8K的| 40 |直接RDRAM的- 288M |
| 文件頁數(shù)： | 28/64頁 |
| 文件大?。?/td> | 4542K |
| 代理商： | HY5R288HC |
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28
Rev.0.9/Dec.2000
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
Initialization
Initialization refers to the process that a controller must go through
after power is applied to the system or the system is reset. The
controller prepares the RDRAM sub-system for normal Channel
operation by using a sequence of control register transactions on
the serial CMOS pins. The following subsystem compo-
nents(including the RDRAM components)during initialization.
This sequence is available in the form of reference code.
1.0 Start Clocks
- This step calculates the proper clock frequencies
for PC1k(controller logic), SynC1k(RAC block), RefC1k(DRCG
component), CTM(RDRAM component) and SCK(SIO block)
2.0 RAC Initialization
- This step causes the INIT block to
generate a RAC, performs RAC maintainance operations and
measures timing intervals in order to ensure clock stability.
3.0 RDRAM Initialization
- This stage performs most of the steps
needed to RDRAMs. The rest are performed in stages 5.0, 6.0 and
7.0. All of the steps in3.0 are carried out through the SIO block
interface.
o 3.1/3.2 SIO Reset
- This reset operation is performed
before any SIO control register read or write transac-
tions. It clears six registers (TEST34, CCA, CCB, SKIP,
TEST78 and TEST79) and places the INIT register into a
special state (all bits cleares except SKP and SDEVID
fields are set to ones). CMD and SIO must be held low
until SIOReset.
o 3.3 Write TEST77 Register
- TEST77 register must be
explicitly written with zeros bdfore any other registers are read
or written.
o 3.4 Write TCYCLE Register
- The TCYCLE register is
written with the CTM clock(for Channel and RDRAMs) in
units of 64ps. The tCYCLE value is determined in stage 1.0.
o 3.5 Write SDEVID Register
- The SDEVID (serial device
identification) register of each RDRAM is written with a
unique address value so that directed SIO read and write trans-
actions can be performed. This address value increases form 0
to 31 according to the distance an RDRAM is from the ASIC
component on the SIO bus(the closest RDRAM is address 0).
o 3.6 Write Devid Register
- The DEVID (device identifica-
tion) register of each RDRAM is written with a unique address
value so that directed memory read and write transactions can
be performed. This address value increases from 0 to 31. The
DeVID value is not necessarily the same as the RDRAMs are
sorted into regions of the same core configuration (number of
bank, row and column address bits and core type).
o 3.7 Write PDNX, PDNXA Registers
- The PDNX and
PDNXA registers are written with values that are used to
measure the timing intervals connected with an exit from the
PDN(powerdown) power state.
o 3.8 Write NAPX Register
- The NAPX register is written
with values that are used to measure the timing intervals
connected with an exit from the NAP power state.
o3.9 Write TPARM Register
- The TPARM register is written
with values whitch determine the time interval between a COL
packet with a memory read command and the Q packet with the
read data on the Channel. The values written set each RDRAM
to the minimum value permitted for the system. This will be
adjusted later in stage 6.0.
o 3.10 Write TCDLY1 Register
- The TCDLY1 register is
written with values which determine the time interval between
a COL packet with a memory read command and thd Qpacket
with the read data on the Channel . The values written set each
RDRAM to the minimum value permitted for the system. This
will be adjusted later in stage 6.0.
o 3.11 Write TFRM Register
- The TFRM register is written
with a value tRDC parameter is the time interval between a
ROW packet with an activate command and the COL packet
with a read or write command.
o 3.12 SETR / CLRR
- First write the following registers with
the indicated values:
TEST78 <= 0004
16
TEST34 <= 0040
16
Next, each RDRAM is given a SETR command and a CLRR
command through the SIO block. This sequence performs a
second reset operation on the RDRAMs. Then the TEST34 and
TEST78 registers are rewritten with zero, in that order.
Figure 26: SIO Reset Sequence
SCK
CMD
SIO0
T
16
0000000000000000
00000000...00000000
0000000000000000
1100
SIO1
T
0
The packet is repeated
from SIO0 to SIO1
1
1
1
1
0
0
0
0
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