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參數(shù)資料
| 型號： | IDT77V1254L25L25PGI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks |
| 中文描述： | 四端口PHY（實體層）為25.6和51.2 ATM網(wǎng)絡(luò) |
| 文件頁數(shù)： | 14/47頁 |
| 文件大小： | 840K |
| 代理商： | IDT77V1254L25L25PGI |
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September 21, 2001
IDT77V1254L25
The output of the 4b/5b encoder provides serial data to the NRZI
encoder. The NRZI code transitions the wire voltage each time a '1' bit is
sent. This, together with the previous encoding schemes guarantees
that long run lengths of either '0' or '1's are prevented. Each symbol is
shifted out with its most significant bit sent first.
When no cells are available to transmit, the 77V1254L25 keeps the
line active by continuing to transmit valid symbols. But it does not
transmit another start-of-cell command until it has another cell for trans-
mission. The 77V1254L25 never generates idle cells.
Transmit HEC Byte Calculation/Insertion
Byte #5 of each ATM cell, the HEC (Header Error Control) is calcu-
lated automatically across the first 4 bytes of the cell header, depending
upon the setting of bit 5 of registers 0x03, 0x13, 0x23 and 0x33. This
byte is then either inserted as a replacement of the fifth byte transferred
to the PHY by the external system, or the cell is transmitted as received.
A third operating mode provides for insertion of
"Bad" HEC codes which may aid in communication diagnostics. These
modes are controlled by the LED Driver and HEC Status/Control Regis-
ters.
Receiver Description
The receiver side of the TC sublayer operates like the transmitter, but
in reverse. The data is NRZI decoded before each symbol is reassem-
bled. The symbols are then sent to the 5b/4b decoder, followed by the
Command Byte Interpreter, De-Scrambler, and finally through a FIFO to
the UTOPIA or DPI interface to an ATM Layer device.
ATM Cell Format
Note that although the IDT77V1254L25 can detect symbol and HEC
errors, it does not attempt to correct them.
Upon reset or the re-connect, each port's receiver is typically not
symbol-synchronized. When not symbol-synchronized, the receiver will
indicate a significant number of bad symbols, and will deassert the Good
Signal Bit as described below. Synchronization is established immedi-
ately once that port receives an Escape symbol, usually as part of the
start-of-cell command byte preceding the first received cell.
The IDT77V1254L25 monitors line conditions and can provide an
interrupt if the line is deemed 'bad'. The Interrupt Status Registers
(registers 0x01, 0x11, 0x21 and 0x31) contain a Good Signal Bit (bit 6,
;00 20
;00 20
;00 20
;00 20 "
9-
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9- 980 0<540 -50 ;
.
set to 0 = Bad signal initially) which shows the status of the line per the
following algorithm:
To declare 'Good Signal' (from "Bad" to "Good")
There is an up-
down counter that counts from 7 to 0 and is initially set to 7. When the
clock ticks for 1,024 cycles (32MHz clock, 1,024 cycles = 204.8
symbols) and no "bad symbol" has been received, the counter
decreases by one. However, if at least one "bad symbol" is detected
during these 1,024 clocks, the counter is increased by one, to a
maximum of 7. The Good Signal Bit is set to 1 when this counter
reaches 0. The Good Signal Bit could be set to 1 as quickly as 1,433
symbols (204.8 x 7) if no bad symbols have been received.
To declare 'Bad Signal' (from "Good" to "Bad")
The same up-
down counter counts from 0 to 7 (being at 0 to provide a "Good" status).
When the clock ticks for 1,024 cycles (32MHz clock, 1,024 cycles =
204.8 symbols) and there is at least one "bad symbol", the counter
increases by one. If it detects all "good symbols" and no "bad symbols"
in the next time period, the counter decreases by one. The "Bad Signal"
is declared when the counter reaches 7. The Good Signal Bit could be
set to 0 as quickly as 1,433 symbols (204.8 x 7) if at least one "bad
symbol" is detected in each of seven consecutive groups of 204.8
symbols.
8kHz Timing Marker
The 8kHz timing marker, described earlier, is a completely optional
feature which is essential for some applications requiring synchroniza-
tion for voice or video, and unnecessary for other applications. Figure 7
shows the options available for generating and receiving the 8kHz
timing marker.
The source of the marker is programmable in the RXREF and
TXREF Control Register (0x40). Each port is individually programmable
to either a local source or a looped remote source. The local source is
TXREF, which is an 8kHz clock of virtually any duty cycle. When
unused, TXREF should be tied high. Also note that it is not limited to
8kHz, should a different frequency be desired. When looped, a received
X_8 command byte causes one to be generated on the transmit side.
A received X_8 command byte causes the 77V1254L25 to issue a
negative pulse on RXREF. The source channel of the marker is
programmable.
PHY-ATM Interface
The 77V1254L25 PHY offers three choices in interfacing to ATM
layer devices such as segmentation and reassembly (SAR) and
switching chips. MODE[1:0] are used to select the configuration of this
interface, as shown in the table below.
UTOPIA is a Physical Layer to ATM Layer interface standardized by
the ATM Forum. It has separate transmit and receive channels and
specific handshaking protocols. UTOPIA Level 2 has dedicated address
signals for both the transmit and receive directions that allow the ATM
layer device to specify with which of the four PHY channels it is commu-
nicating. UTOPIA Level 1 does not have address signals.
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