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參數(shù)資料
| 型號： | IDT77V1254L25L25PGI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks |
| 中文描述： | 四端口PHY（實體層）為25.6和51.2 ATM網(wǎng)絡(luò) |
| 文件頁數(shù)： | 26/47頁 |
| 文件大?。?/td> | 840K |
| 代理商： | IDT77V1254L25L25PGI |
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September 21, 2001
IDT77V1254L25
Figure 30 DPI Transmit Handshake - Neither Device Ready
Control and Status Interface
Utility Bus
The Utility Bus is a byte-wide interface that provides access to the registers within the IDT77V1254L25. These registers are used to select desired
operating characteristics and functions, and to communicate status to external systems.
The Utility Bus is implemented using a multiplexed address and data bus (AD[7:0]) where the register address is latched via the Address Latch
Enable (ALE) signal.
The Utility Bus interface is comprised of the following pins: AD[7:0], ALE, CS, RD, WR
Read Operation
Refer to the Utility Bus timing waveforms in Figures 43 and 44. A register read is performed as follows:
1. Initial condition:
–
RD, WR, CS not asserted (logic 1)
–
ALE not asserted (logic 0)
2. Set up register address:
–
place desired register address on AD[7:0]
–
set ALE to logic 1;
–
latch this address by setting ALE to logic 0.
3. Read register data:
–
Remove register address data from AD[7:0]
–
assert CS by setting to logic 0;
–
assert RD by setting to logic 0
–
wait minimum pulse width time (see AC specifications)
Write Operation
A register write is performed as described below:
1. Initial condition:
–
RD, WR, CS not asserted (logic 1)
–
ALE not asserted (logic 0)
2. Set up register address:
–
place desired register address on AD[7:0]
–
set ALE to logic 1;
–
latch this address by setting ALE to logic 0.
3. Write data:
–
place data on AD[7:0]
–
assert CS by setting to logic 0;
–
assert WR (logic 0) for minimum time (according to timing specification); reset WR to logic 1 to complete register write cycle.
Interrupt Operations
The IDT77V1254L25 provides a variety of selectable interrupt and signalling conditions which are useful both during ‘normal’ operation, and as
diagnostic aids. Refer to the Status and Control Register List section.
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'A
54
0
50
0
50
0
50
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:
0
50 "
0
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