參數(shù)資料
型號(hào): IDT77V1254L25L25PGI
廠商: Integrated Device Technology, Inc.
英文描述: Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks
中文描述: 四端口PHY(實(shí)體層)為25.6和51.2 ATM網(wǎng)絡(luò)
文件頁數(shù): 41/47頁
文件大?。?/td> 840K
代理商: IDT77V1254L25L25PGI
41 of 47
September 21, 2001
IDT77V1254L25
Figure 39 UTOPIA Level 1 Transmit
Figure 40 UTOPIA Level 1 Receive
DPI Bus Timing Parameters
t42
RXEN[3:0] Hold Time to RXCLK
1.5
ns
t43
RXCLK to RXCLAV[3:0] Invalid (min) and Valid (max)
2
10
ns
t44
RXCLK to RXSOC High-Z
2
10
ns
t45
RXCLK to RXSOC Low-Z (min) and Valid (max)
2
10
ns
t46
RXCLK to RXDATA, RXPARITY High-Z
2
10
ns
t47
RXCLK to RXDATA, RXPARITY Low-Z (min) and Valid (max)
2
10
ns
Symbol
Parameter
Min.
Max.
Unit
t51
DPICLK Frequency
0.2
50
MHz
t52
DPICLK Duty Cycle (% of t51)
40
60
%
t53
DPICLK to Pn_TCLK Propagation Delay
2
14
ns
t54
Pn_TFRM Setup Time to Pn_TCLK
4
ns
t55
Pn_TFRM Hold Time to Pn_TCLK
1
ns
t56
Pn_TD[3:0] Setup Time to Pn_TCLK
4
ns
t57
Pn_TD[3:0] Hold Time to Pn_TCLK
1
ns
Symbol
Parameter
Min.
Max.
Unit
&
TXEN[3:0]
!>@
!!>$@B
'!()*
+
$
"
#
.0
.0
"
RXEN[3:0]
(!>@
(!!>$@B
('!()*
(
(+
"
&
"
"
"
"
"$
"#
""
"$
"
;56G7
;56G7
;56G7
;56G7
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