參數(shù)資料
型號： IDT77V1254L25L25PGI
廠商： Integrated Device Technology, Inc.
英文描述： Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks
中文描述： 四端口PHY（實體層）為25.6和51.2 ATM網(wǎng)絡
文件頁數(shù)： 17/47頁
文件大?。?/td> 840K
代理商： IDT77V1254L25L25PGI
17 of 47
September 21, 2001
IDT77V1254L25
the transfer of a cell has begun. In every other way the two modes are
identical. Cell mode is the default configuration and is the one described
later.
The Utopia 1 signals are summarized below:
Transmit and receive both utilize free running clocks, which are
inputs to the 77V1254L25. All Utopia signals are timed to these clocks.
In the transmit direction, the PHY first asserts TXCLAV (transmit cell
available) to indicate that it has room in its transmit FIFO to accept at
least one 53-byte ATM cell. When the ATM layer device is ready to
begin
passing the cell, it asserts TXEN (transmit enable) and TXSOC (start of
cell), coincident with the first byte of the cell on TXDATA. TXEN remains
asserted for the duration of the cell transfer, but the ATM device may
deassert TXEN at any time once the cell transfer has begun, but data is
transferred only when TXEN is asserted.
In the receive direction, RXEN indicates when the ATM device is
prepared to receive data. As with transmit, it may be asserted or deas-
serted at any time. Note, however, that not more than one RXEN should
be asserted at a time. Also, once a given RX port is selected, that port's
FIFO must be emptied of cells (as indicated by RXCLAV) before a
different RX port may be enabled.
In both transmit and receive, TXSOC and RXSOC (start of cell) is
asserted for one clock, coincident with the first byte of each cell. Odd
parity is utilized across each 8-bit data field.
Figure 8 shows the data sequence for an ATM cell over Utopia Level
1, and Figures 15 to 21 are examples of the Utopia Level 1 handshake.
TXDATA[7:0]
TXPARITY
TXSOC
TXEN
[3:0]
TXCLAV[3:0]
ATM to PHY
ATM to PHY
ATM to PHY
ATM to PHY
PHY to ATM
ATM to PHY
TXCLK
RXDATA[7:0]
RXPARITY
RXSOC
PHY to ATM
PHY to ATM
PHY to ATM
ATM to PHY
RXEN
[3:0]
RXCLAV[3:0]
PHY to ATM
ATM to PHY
RXCLK
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