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參數(shù)資料
| 型號： | IDT77V1254L25L25PGI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks |
| 中文描述： | 四端口PHY（實體層）為25.6和51.2 ATM網(wǎng)絡(luò) |
| 文件頁數(shù)： | 16/47頁 |
| 文件大小： | 840K |
| 代理商： | IDT77V1254L25L25PGI |
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September 21, 2001
IDT77V1254L25
Instead, key handshaking signals are duplicated so that each
channel has its own signals. In both versions of UTOPIA, all channels
share a single transmit data bus and a single receive data bus for data
transfer.
DPI is a low-pin count Physical Layer to ATM Layer interface. The
low-pin count characteristic allows the 77V1254L25 to incorporate four
separate DPI 4-bit ports, one for each of the four serial ports. As with the
UTOPIA interfaces, the transmit and receive directions have their own
data paths and handshaking.
UTOPIA Level 2 Interface option
The 16-bit Utopia Level 2 interface operates as defined in ATM
Forum document af-phy-0039. This PHY-ATM interface is selected by
setting the MODE[1:0] pins both low.
This mode is configured as a single 16-bit data bus in the transmit
(ATM-to-PHY) direction, and a single 16-bit data bus in the receive
(PHY-to-ATM) direction. In addition to the data bus, each direction also
includes a single optional parity bit, an address bus, and several hand-
shaking signals. The UTOPIA address of each channel is determined by
bits 4 to 0 in the Enhanced Control Registers. Please note that the
transmit bus and the receive bus operate completely independently. The
Utopia 2 signals are summarized below:
To determine if any of them has room to accept a cell for transmis-
sion (TXCLAV), or has a receive cell available to pass on to the ATM
device (RXCLAV). To poll, the ATM device drives an address (TXADDR
or RXADDR) then observes TXCLAV or RXCLAV on the next cycle of
TXCLK or RXCLK. A port must tri-state TXCLAV and RXCLAV except
when it is addressed.
If TXCLAV or RXCLAV is asserted, the ATM device may select that
port, then transfer a cell to or from it. Selection of a port is performed by
driving the address of the desired port while TXEN or RXEN is high,
TXDATA[15:0]
ATM to PHY
TXPARITY
ATM to PHY
TXSOC
ATM to PHY
TXADDR[4:0]
ATM to PHY
TXEN
ATM to PHY
TXCLAV
PHY to ATM
TXCLK
ATM to PHY
RXDATA[15:0]
RXPARITY
RXSOC
RXADDR[4:0]
PHY to ATM
PHY to ATM
PHY to ATM
ATM to PHY
ATM to PHY
PHY to ATM
RXEN
RXCLAV
RXCLK
ATM to PHY
then driving TXEN or RXEN low. When TXEN is driven low, TXSOC
(start of cell) is driven high to indicate that the first 16 bits of the cell are
being driven on TXDATA. The ATM device may chose to temporarily
suspend transfer of the cell by deasserting TXEN. Otherwise, TXEN
remains asserted as the next 16 bits are driven onto TXDATA with each
cycle of TXCLK.
In the receive direction, the ATM device selects a port if it wished to
receive the cell that the port is holding. It does this by asserting RXEN.
The PHY then transfers the data 16 bits each clock cycle, as deter-
mined by RXEN. As in the transmit direction, the ATM device may
suspend transfer by deasserting RXEN at any time. Note that the PHY
asserts RXSOC coincident with the first 16 bits of each cell.
TXPARITY and RXPARITY are parity bits for the corresponding 16-
bit data fields. Odd parity is used.
Figure 9 through Figure 14 may be referenced for Utopia 2 bus
examples.
Because this interface transfers an even number of bytes, rather
than the ATM standard of 53 bytes, a filler byte is inserted between the
5-byte header and the 48-byte payload. This is shown in Figure 8.
UTOPIA Level 1 multi-phy interface Option
The UTOPIA Level 1 MULTI-PHY interface is based on ATM Forum
document af-phy-0017. Utopia Level 1 is essentially the same as Utopia
Level 2, but without the addressing, polling and selection features.
Figure 6 Utopia Level 2 Data Format and Sequence
Instead of addressing, this mode utilizes separate TXCLAV, TXEN,
RXCLAV and RXEN signals for each channel of the 77V1254L25. There
are just one each of the TXSOC and RXSOC signals, which are shared
across all four channels.
In addition to Utopia Level 2's cell mode transfer protocol, Utopia
Level 1 also offers the option of a byte mode protocol. Bit 1 of the
Master Control Registers is used to program whether the UTOPIA Level
1 bus is in cell mode or byte mode. In byte mode, the PHY is allowed to
control data transfer on a byte-by-byte basis via the TXCLAV and
RXCLAV signals. In cell mode, TXCLAV and RXCLAV are ignored once
;00 0
;00 0
;00 0
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' 0
' 0
' 0 "
;00 0
;00 0 "
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' 0
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' 0 #
' 0 "#
' 0 "$
'0 "%
25
25
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