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| 型號： | IDT77V1254L25L25PGI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks |
| 中文描述： | 四端口PHY（實體層）為25.6和51.2 ATM網(wǎng)絡(luò) |
| 文件頁數(shù)： | 32/47頁 |
| 文件大?。?/td> | 840K |
| 代理商： | IDT77V1254L25L25PGI |
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September 21, 2001
IDT77V1254L25
Line Side (Serial) Interface
Each of the four ports has two pins for differential serial transmission, and two pins for differential serial receiving.
PHY to Magnetics Interface
A standard connection to 100
and 120
unshielded twisted pair cabling is shown in Figure 36. Note that the transmit signal is somewhat attenu-
ated in order to meet the launch amplitude specified by the standards. The external receive circuitry is designed to attenuate low frequencies in order
to compensate for the high frequency attenuation of the cable.
Also, the receive circuitry biases the positive and negative RX inputs to slightly different voltages. This is done so that the receiver does not receive
false signals in the absence of a real signal. This can be important because the 77V1254L25 does not disable error detection or interrupts when an
input signal is not present.
When connecting to UTP at 51.2 Mbps, it is necessary to use magnetics with sufficient bandwidth. Such a device can also operate satisfactorily at
25.6 Mbps. Refer to Table 5 for the recommended magnetics.
Figure 36 Recommended Connection to Magnetics
Component
Value
Tolerance
R1
47
±5%
R2
47
±5%
R3
620
±5%
R4
110
±5%
R5
2700
±5%
R6
2700
±5%
R7
82
±5%
R8
33
±5%
R9
33
±5%
Table 4 Analog Component Values (Part 1 of 2)
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