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參數(shù)資料
| 型號： | IDT77V1254L25L25PGI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks |
| 中文描述： | 四端口PHY（實體層）為25.6和51.2 ATM網(wǎng)絡(luò) |
| 文件頁數(shù)： | 45/47頁 |
| 文件大?。?/td> | 840K |
| 代理商： | IDT77V1254L25L25PGI |
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45 of 47
September 21, 2001
IDT77V1254L25
AC Test Conditions
Figure 46 Output Load
A note about Figures 47 and 48: The ATM Forum and ITU-T standards for 25 Mbps ATM define "Network" and "User" interfaces. They are identical
except that transmit and receive are switched between the two. A Network device can be connected directly to a User device with a straight-through
cable. User-to-User or Network-to-Network connections require a cable with 1-to-7 and 2-to-8 crossovers.
Figure 47 PC Board Layout for ATM Network
Note:
1.No power or ground plane inside this area.
2.Analog power plane inside this area.
3.Digital power plane inside this area.
4.A single ground plane should extend over the area covered by the analog and digital power planes, without breaks.
5.All analog signal traces should avoid 90° corners.
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figure 46
900
1.2K
3.3V
30pF*
* Includes jig and scope capacitances.
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