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參數(shù)資料
| 型號： | IDT77V1254L25L25PGI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks |
| 中文描述： | 四端口PHY（實(shí)體層）為25.6和51.2 ATM網(wǎng)絡(luò) |
| 文件頁數(shù)： | 35/47頁 |
| 文件大?。?/td> | 840K |
| 代理商： | IDT77V1254L25L25PGI |
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35 of 47
September 21, 2001
IDT77V1254L25
LED Driver and HEC Status/Control Registers
6
R/W
0 = UTOPIA
RXCLAV Operation Select -
(for Utopia 1 mode) The UTOPIA standard dictates that during cell mode operation, if the
receive FIFO no longer has a complete cell available for transfer from PHY, RXCLAV is deasserted following transfer of
the last byte out of the PHY to the upstream system. With this bit set, early deassertion of this signal will occur coinci-
dent with the end of Payload byte 44 (as in octet mode for TXCLAV). This provides early indication to the upstream
system of this impending condition.
0 = "Standard UTOPIA RXCLAV’
1 = "Cell mode = Byte mode"
5
R/W
1 = tri-state
Single/Multi-PHY configuration select -
(applicable and writable only in Utopia 1 mode)
0 = single: Never tri-state RXDATA, RXPARITY and RXSOC
1 = Multi-PHY mode: Tri-state RXDATA, RXPARITY and RXSOC when RXEN = 1
4
R/W
0 = normal
RFLUSH = Clear Receive FIFO -
This signal is used to tell the TC to flush (clear) all data in the receive FIFO. The TC
signals this completion by clearing this bit.
3
R/W
0 = normal
Insert Transmit Payload Error -
Tells TC to insert cell payload errors in transmitted cells. This can be used to test
error detection and recovery systems at destination station, or, under loopback control, at the local receiving station.
This payload error is accomplished by flipping bit 0 of the last cell payload byte.
2
R/W
0 = normal
Insert Transmit HEC Error -
Tells TC to insert HEC error in Byte 5 of cell. This can be used to test error detection and
recovery systems in downstream switches, or, under loopback control, the local receiving station. The HEC error is
accomplished by flipping bit 0 of the HEC byte.
1,0
R/W
00 = normal
Loopback Control
bit # 1 0
0 0 Normal mode (receive from network)
1 0 PHY Loopback
1 1 Line Loopback
Addresses: 0x03, 0x13, 0x23, 0x33
Bit
Type
Initial State
Function
7
0
Reserved
6
R/W
0 = enable checking
Disable Receive HEC Checking (HEC Enable) -
When not set, the HEC is calculated on first 4 bytes of received cell,
and compared against the 5th byte. When set (= 1), the HEC byte is not checked.
5
R/W
0 = enable calculate &
replace
Disable Transmit HEC Calculate & Replace -
When set, the 5th header byte of cells queued for transmit is not
replaced with the HEC calculated across the first four bytes of that cell.
4, 3
R/W
00 = 1 cycle
RXREF Pulse Width Select
bit # 4 3
0 0 RXREF active for 1 OSC cycle
0 1 RXREF active for 2 OSC cycles
1 0 RXREF active for 4 OSC cycles
1 1 RXREF active for 8 OSC cycles
2
R
1 = empty
FIFO Status
1 = TxFIFO empty 0 = TxFIFO not empty
1
R
1
TXLED Status
0 = Cell Transmitted 1 = Cell Not Transmitted
0
R
1
RXLED Status
0 = Cell Received 1 = Cell Not Received
Addresses: 0x02, 0x12, 0x22, 0x32
Bit
Type
Initial State
Function
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