參數(shù)資料
型號(hào): IDT77V1254L25L25PGI
廠(chǎng)商: Integrated Device Technology, Inc.
英文描述: Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks
中文描述: 四端口PHY(實(shí)體層)為25.6和51.2 ATM網(wǎng)絡(luò)
文件頁(yè)數(shù): 47/47頁(yè)
文件大?。?/td> 840K
代理商: IDT77V1254L25L25PGI
47 of 47
September 21, 2001
IDT77V1254L25
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-330-1748
www.idt.com
for Tech Support:
email: phyhelp@idt.com
phone: 408-330-1752
Ordering Information
Revision History
3/2/98:
ADVANCE INFORMATION. Initial Draft.
10/5/98
PRELIMINARY. TXOSC pin name changed to OSC. Missing information added. Package code corrected in ordering code.
11/30/98
PRELIMINARY. Numerous minor edits. Corrections to Figures 26 and 30. Elimination of Line Rate Selection bit in the Master Control
Registers. IDD1 and IDD2 values updated. Addition of VPI/VCI Swap feature. Improvements to Utopia bus timing parameters.
3/23/99:
Update to new format, revisions to Utopia 1 text.
3/8/01
Changed from Preliminary to Final. Various typographic corrections. Corrected default values for UTOPIA 2 Port Address in the
Enhanced Control 1 Registers. Added IDD values for 51 Mbps.Removed Trd minimum spec. IDD Values for 25 Mbps and 51 Mbps
updated.
9/21/2001
Changed values in the Max. column for IDD1 and IDD2 in the DC Electrical Characteristics (All pins except TX and RX) table.
Changed value in Max. column for t23 in Utopia Level 2 Bus Timing Parameters table. Added Loop Timing Feature section.
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