參數(shù)資料
型號(hào)： IDT77V1254L25L25PGI
廠商： Integrated Device Technology, Inc.
英文描述： Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks
中文描述： 四端口PHY（實(shí)體層）為25.6和51.2 ATM網(wǎng)絡(luò)
文件頁(yè)數(shù)： 34/47頁(yè)
文件大小： 840K
代理商： IDT77V1254L25L25PGI
34 of 47
September 21, 2001
IDT77V1254L25
Master Control Registers
Interrupt Status Registers
Diagnostic Control Registers
Addresses: 0x00, 0x10, 0x20, 0x30
Bit
Type
Initial State
Function
7
R/W
0
Reserved
6
R/W
1 = discard errored cells
Discard Receive Error Cells -
On receipt of any cell with an error (e.g. short cell, invalid command mnemonic, receive
HEC error (if enabled), this cell will be discarded and will not enter the receive FIFO.
5
R/W
0 = all interrupts
Enable Cell Error Interrupts Only -
If Bit 0 in this register is set (Interrupts Enabled), setting of this bit enables only
"Received Cell Error" (as defined in bit 6) to trigger interrupt line.
4
R/W
0 = disabled
Transmit Data Parity Check -
Directs TC to check parity of TXDATA against parity bit located in TXPARITY.
3
R/W
1 = discard idle cells
Discard Received Idle Cells -
Directs TC to discard received idle (VPI/VCI = 0) cells from PMD without signalling
external systems.
2
R/W
0 = not halted
Halt Transmit -
Halts transmission of data from TC to PMD and forces the TXD outputs to the "0" state
1
R/W
0 = cell mode
UTOPIA Level 1 mode select: -
0 = cell mode, 1 = byte mode. Not applicable for Utopia 2 or DPI modes.
0
R/W
1 = enable interrupts
Enable Interrupt Pin (Interrupt Mask Bit) -
Enables interrupt output pin (pin 85). If cleared, pin is always high and
interrupt is masked. If set, an interrupt will be signaled by setting the interrupt pin to "0". It doesn’t affect the Interrupt
Status Registers.
Addresses: 0x01, 0x11, 0x21, 0x31
Bit
Type
Initial State
Function
7
Reserved
6
R
0 = Bad Signal
Good Signal Bit -
See definition on page 13.
1 - Good Signal
0 - Bad Signal
5
sticky
0
HEC error cell received -
Set when a HEC error is detected on received cell.
4
sticky
0
"Short Cell" Received -
Interrupt signal which flags received cells with fewer than 53 bytes. This condition is detected
when receiving Start-of-Cell command bytes with fewer than 53 bytes between them.
3
sticky
0
Transmit Parity Error -
If Bit 4 of Register 0x00 / 0x10 / 0x20 / 0x30 is set (Transmit Data Parity Check), this interrupt
flags a transmit data parity error condition. Odd parity is used.
2
sticky
0
Receive Signal Condition change -
This interrupt is set when the received ’signal’ changes either from ’bad to good’
or from ’good to bad’.
1
sticky
0
Received Symbol Error -
Set when an undefined 5-bit symbol is received.
0
sticky
0
Receive FIFO Overflow -
Interrupt which indicates when the receive FIFO has filled and cannot accept additional data.
Addresses: 0x02, 0x12, 0x22, 0x32
Bit
Type
Initial State
Function
7
R/W
0 = normal
Force TXCLAV deassert -
(applicable only in Utopia 1 and 2 modes) Used during line loopback mode to prevent
upstream system from continuing to send data to the 77V1254L25.
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