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參數(shù)資料
| 型號： | IDT77V1254L25L25PGI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks |
| 中文描述： | 四端口PHY（實(shí)體層）為25.6和51.2 ATM網(wǎng)絡(luò) |
| 文件頁數(shù)： | 30/47頁 |
| 文件大?。?/td> | 840K |
| 代理商： | IDT77V1254L25L25PGI |
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September 21, 2001
IDT77V1254L25
Jitter in Loop Timing Mode
One of the primary concerns when using loop timing mode is the amount of jitter that gets added each time data is transmitted. Table 3 shows the
jitter measured at various data rates. The set-up shown in Figure 35 was used to perform these tests. The maximum jitter seen was at TX point 5 and
the minimum jitter was at point 2. The loop timing jitter is defined as the amount of jitter generated by each TX node. In other words, the loop timing
jitter or the jitter added by a loop-timed port in the set-up below is the difference between the Total Output Jitter and the Total Input Jitter.
Figure 35 Test Setup for Loop Timing Jitter Measurements
Loop Timing Jitter Specification
The waveforms below show some of the measurements taken with the set-up in Figure 35. Using the formula above, the jitter specification was
derived. For example, at data rate of 25.6Mbps, jitter added going through Line Card 3 is 1.5ns -1.4ns (as shown in the waveforms below).
Line Rate
Mbps
Data Rate
Mbps
Min.
Typ.
Max.
Note
32
25.6
--
100 ps
--
Using 32Mhz OSC
64
51.2
--
100 ps
--
Using 64Mhz OSC
Table 3 Loop Timing Jitter
Data
Data
Data
Data
Data
Data
SWITCH
Loop Timing Mode
Loop Timing Mode
Loop Timing Mode
P1
P2
P3
CLK
CLK
CLK
RX
RX
RX
TX
TX
TX
TX
RX
Normal Mode
P0
OSC
1
2
3
4
5
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