參數(shù)資料
型號： IDT88P8344BHGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820
封裝： GREEN, PLASTIC, BGA-820
文件頁數(shù)： 11/98頁
文件大?。?/td> 601K
代理商： IDT88P8344BHGI
11
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
Generic Name
Specific Name
I/O type
Description
Mode
Link
RDCLK
PHY
I_DCLK (P & N) SPI4_I_DCLK_P
I LVDS
Ingress data clock
TDCLK
SPI4_I_DCLK_N
SPI4_I_DAT_P[15:0]
SPI4_I_DAT_N[15:0]
I_DAT[15:0]
(P & N)
I_CRTL (P & N) SPI4_I_CTRL_P
I LVDS
Ingress data bus
RDAT
TDAT
I LVDS
Ingress control word
RCTL
TCTL
SPI4_I_CTRL_N
SPI4_I_SCLK_P
SPI4_I_SCLK_N
SPI4_I_STAT_P[1:0]
SPI4_I_STAT_N[1:0]
SPI4_I_SCLK_T
SPI4_I_STAT_T[1:0]
BIAS
I_SCLK_L
(P & N)
I_STAT_L[1:0]
(P & N)
I_SCLK_T
I_STAT_T[1:0]
BIAS
O LVDS
Ingress status clock
RSCLK
TSCLK
O LVDS
Ingress status info
RSTAT
TSTAT
O LVTTL Ingress status clock
O LVTTL Ingress status info
Analog
Use an external 3K Ohm
1% resistor to VSS
I-PU
LVDS(high)/LVTTL (low) status
selection (See Note below)
RSCLK
RSTAT
----------
TSCLK
TSTAT
----------
LVDS_STA
LVDS_STA
----------
----------
TABLE 5 – SPI-4 INGRESS INTERFACE DEFINITION
Generic Name
Specific Name
I/O type
Description
Mode
Link
PHY
E_DCLK (P & N) SPI4_E_DCLK_P
O LVDS Egress data clock
TDCLK
RDCLK
SPI4_E_DCLK_N
SPI4_E_DAT_P[15:0]
SPI4_E_DAT_N[15:0]
E_DAT[15:0]
(P & N)
E_CRTL (P & N) SPI4_E_CTRL_P
O LVDS
Egress data bus
TDAT[15:0] RDAT[15:0]
O LVDS
Egress control word
TCTL
RCTL
SPI4_E_CTRL_N
SPI4_E_SCLK_P
SPI4_E_SCLK_N
SPI4_E_STAT_P[1:0]
SPI4_E_STAT_N[1:0]
SPI4_E_SCLK_T
SPI4_E_STAT_T[1:0] I-PU LVTTLEgress status info
E_SCLK_L
(P & N)
E_STAT_L[1:0]
(P & N)
E_SCLK_T
E_STAT_T[1:0]
I LVDS
Egress status clock
TSCLK
RSCLK
I LVDS
Egress status info
TSTAT[1:0] RSTAT[1:0]
I-ST LVTTL Egress status clock
TSCLK
TSTAT
RSCLK
RSTAT[1:0]
TABLE 6 – SPI-4 EGRESS INTERFACE DEFINITION
SPI-4 (one instantiation)
For the SPI-4 interface, each pin is used differently depending whether the
SPI-4 is in Link mode or in PHY mode. The pin is given a generic name, shown
in the Name column, and mapped to the OIF standard pin name according to
the mode of operation of the interface (Link to PHY).
NOTE
:
1. A hardware reset or software reset must be performed after changing the level of this pin.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT88P8344BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT89H10T4BG2ZBBC 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA
IDT89H10T4BG2ZBBC8 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA
IDT89H10T4BG2ZBBCG 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT89H10T4BG2ZBBCG8 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA
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