參數(shù)資料
型號(hào)： IDT88P8344BHGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820
封裝： GREEN, PLASTIC, BGA-820
文件頁數(shù)： 84/98頁
文件大?。?/td> 601K
代理商： IDT88P8344BHGI
84
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
Inputs
Duty cycle
Frequency (DDR)
Frequency (DDR)
TR, TF
Deskew
Outputs
Duty cycle
Frequency (DDR)
Frequency (DDR)
TR, TF
Tskew
SYNTH Jitter
TD
Unit
%
MHz
MHz
ps
UI
Mn.
45
80
200
300
—
Typ.
50
—
311
—
—
Max.
55
200
400
500
+/- 1
Description
I_DCLK ingress clock duty cycle
Ingress clock frequency, I_LOW=1
Ingress clock frequency, I_LOW=0
Input rise or fall time ( 20%, 80% )
Bit line deskew
%
MHz
MHz
ps
ps
UI
ns
45
80
200
300
—
—
—
50
—
311
—
—
—
—
55
200
400
500
50
0.1
—
E_DCLK Egress clock duty cycle
Egress clock frequency, E_LOW=1
Egress clock frequency, E_LOW=0
Output rise or fall time ( 20%, 80% )
Output differential skew, P to N
PLL jitter as a fraction of the clock cycle
Adjustable
TABLE 133 – SPI-4.2 LVDS AC INPUT / OUTPUT TIMING SPECIFICATIONS
REF_CLK
Duty cycle
F
REF_CLK
T
R
, T
F
Unit
%
MHz
ns
Mn.
30
12.5
—
Typ.
50
19.44
—
Max.
70
25
5
REF_CLK clock input duty cycle
Main reference clock input
Rise fall time ( 20%, 80% )
11.6.4 REF_CLK clock input
TABLE 135 – REF_CLK CLOCK INPUT
11.6.5 MCLK internal clock and OCLK[3:0] clock outputs
TABLE 136 – OCLK[3:0] CLOCK OUTPUTS AND MCLK INTERNAL CLOCK
OCLK[3:0]
Duty cycle
Frequency
Output skew
between OCLKs
T
R
, T
F
MCLK
Frequency
Unit
%
MHz
Mn.
45
40
Typ.
50
104
Max.
55
133
Description
OCLK[3:0] outputs, clock duty cycle
OCLK[3:0], programmable
One pll_oclk cycle of deliberate
skew between each OCLK[3:0]
OCLK[3:0] rise, fall time (20%,80%)
ns
1
2
MHz
80
—
100
Programmable
11.6.6 Microprocessor interface
TABLE 137 – MICROPROCESSOR INTERFACE
All outputs
T
R
, Tf
All inputs
T
R
, T
F
Unit
ns
Mn.
Typ.
Max.
10
Description
Rise, fall time (20%, 80%)
ns
10
Rise, fall time (20%,80%)
Parameter
Symbol
Conditions
Mn
Typ
Max
Unit
SPI-4 LVTTL Status
(1)
STAT_T[1:0] to SCLK_T setup time
SCLK_T to STAT_T [1:0] hold time
SCLK_T to STAT_T [1:0] delay
NOTE:
1. For the SPI-4 LVTTL valid, hold & setup the edge is configurable. The SPI-4 ingress LVTTL status clock active edge is
configured by I_CLK_EDGE field in Table 89-SPI-4 Ingress Configuration Register on page 69. The SPI-4 egress LVTTL
status clock active edge is configured by E_CLK_EDGE field in Table 104-SPI-4 Egress Configuration Register on page 73.
T
SU
T
H
T
D
2
ns
ns
ns
0.5
1
1.2
11.6.3 SPI-4 LVTTL Status AC characteristics
TABLE 134 – SPI-4 LVTTL STATUS AC CHARACTERISTICS
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