參數(shù)資料
型號： IDT88P8344BHGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820
封裝： GREEN, PLASTIC, BGA-820
文件頁數(shù)： 19/98頁
文件大?。?/td> 601K
代理商： IDT88P8344BHGI
19
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
Manual phase selection
The automatic phase adjustment can be overruled by the processor when
the FORCE flag is set see Table 99, SPI-4 ingress bit alignment control register
(register_offset 0x11). The PHASE_ASSIGN field see Table 113, SPI-4
ingress manual alignment phase/result register (0x0C to 0x1F) now defines the
selected phase.
Word alignment
The de-skew block searches for the Training Control Word 0x0FFF. If the
Training Control Word is found, then training data is expected to follow the
Training Control Word. The orthogonal training data will be used to align the
word.
A de-skew control bit (I_DSC in Table 89-SPI-4 ingress configuration register
at Block_base 0x0300 + Register_offset 0x00) is used to protect against a
randomdata error during de-skew. If I_DSC=1, then two consecutive de-skew
results are required. It is recommended to set I_DSC to 1.
For diagnostics, an out of range offset between lines is provided. If the offset
is more than two bits between the earliest and latest samples, I_DSK_OOR is
set to a logic one. I_DSK_OOR is cleared to a logic zero when the offset is in
range.
Transfer decode and dispatch
In the
OUT_OF_SYNCH
state, the de-skew block will decode the transfer,
and check the DIP-4 for validation.
A number of consecutive error free DIP-4 ingress bursts will lead to a transition
to the IN_SYNCH. The number is defined by the I_INSYNC_THR field in Table
89-SPI-4 ingress configuration register (Block_base 0x0300 + Register_offset
0x00).
In the
IN_SYNCH
state, the PFP decodes the status transfer, check the DIP-
4, and dispatches the data.
A number of consecutive DIP-4 errors will lead to the OUT_OF_SYNCH
state. The number is defined by the I_OUTSYNC_THR field in Table 89-SPI-
4 ingress configuration register (Block_base 0x0300 + Register_offset 0x00).
A number of consecutive training patterns will lead to OUT_OF_SYNCH.
The number is defined by the STRT_TRAIN field in the Table 100 SPI-4 ingress
start up training threshold register (Block_base 0x0300 + Register_offset 0x12).
This feature is disabled if STRT_TRAIN=0.
Control word and data
A control word is distinguished by the SPI-4 RTCL signal. (logic one = control
word).
DIP-4 check
For the DIP-4 check algorithmrefer to the OIF SPI-4 document [Glossary].
In both IN_SYNCH and OUT_OF_SYNCH states, only control word previous
and following data is checked. Any transition on synch status will be captured.
In IN_SYNCH state, each DIP-4 error is captured and counted.
IN_SYNCH
OUT_OF_SYNCH
A= A number of consecutive DIP-4 error or reset or interface disabled
or a number of consecutive training pattern received
B= A number of consecutive DIP-4 error free
A
B
6370 drw35
Figure 8. SPI-4 ingress state diagram
Transfer decode
The SPI-4 ingress control word contains various fields. Refer to the OIF SPI-
4 document [Glossary] for details. If reserved control word, BIT[15:12]=0011,
0001, 0101, or 0111 is detected, a BUS_ERROR event is generated. If a
payload control word is not followed by a data word, or a data word does not
follow a payload control word, a BUS_ERROR event is generated. If abort is
detected, the next packet will be tagged with an error.
Data dispatch
The port address field of a payload control word is extracted as a search key.
The search key is used to search the dispatch info in Table 86, SPI-4 ingress
LP to LID map (256 entries, one per LP). If the searched port is active, transfer
data is sent to the associated PFP with SOP, EOP, LENGTH, PACKET_ERROR.
If the searched port is inactive, a SPI4_INACTIVE_TRANSFER event is
generated. A SPI-4 inactive transfer event with it's associated LP will be captured
in the Table 40, SPI-4 status register (0x22 in the direct accessed space).
SPI-4 ingress status channel
Calendar structure and swapping
The SPI Exchange supports one or two sets of calendars. If I_CSW_EN field
in the Table 89, SPI-4 ingress configuration register (0x00)=1, two sets of
calendars are supported. A calendar selection word must be placed following
the framng bit. Refer to the OIF SPI-4 document [see Glossary] for more details.
SPI-4 ingress status channel frame generation
The status frame can be one of the following cases:
All ‘11’ when LVTTL is in the out of synch state
Training pattern when LVDS is in the out of synch state or in periodic training
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT88P8344BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT89H10T4BG2ZBBC 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA
IDT89H10T4BG2ZBBC8 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA
IDT89H10T4BG2ZBBCG 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT89H10T4BG2ZBBCG8 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA
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