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參數(shù)資料
| 型號(hào)： | IDT88P8344BHGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820 |
| 封裝： | GREEN, PLASTIC, BGA-820 |
| 文件頁數(shù)： | 39/98頁 |
| 文件大?。?/td> | 601K |
| 代理商： | IDT88P8344BHGI |
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39
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
6. CLOCK GENERATOR
The device generates clocks fromthe SPI-4 ingress clock (I_DCLK) or from
the REF_CLK input pin. The clock so selected is used for core functions of the
device, and must be present during reset and thereafter. The selection and
frequency divisors are defined by CK_SEL[3:0] pins as defined in the following
Table 14, CK_SEL[3:0] input pin encoding.
The clock generator provides four clock outputs on the OCLK[3:0] pins,
MCLK for internal use, and SPI-4 data and FIFO status channel egress clocks.
The OCLK[3:0] clock frequencies can be selected independently of each other.
OCLK[3:0] outputs always have a relative output skew of one pll_oclk (refer to
Figure 30 Clock generator) to prevent simultaneous switching when used as
SPI-3 clock sources. Use of the OCLK[3:0] outputs is encouraged for the SPI-
3 clock inputs to reduce systemjitter. The frequency is divided according to the
value selected in the clock generator control register shown below. The
OCLK[3:0] pins are separately enabled by setting each associated enable flag
in Table 121, Clock generator control register (Register_offset 0x10). When an
OCLK[3:0] output is not enabled, it is in a logic low state. MCLK is the internal
processing clock, and is always enabled. Divide options should be selected to
keep the internal PLL output pll_oclk within its operating frequency range of 400
to 800 MHZ. Refer to Table 122, OCLK and MCLK frequency select encoding
for selecting the frequencies of MCLK and OCLKs. Note that divider values
should be chosen so that OCLK[3:0] and MCLK are within their specified
operating range provided in Table 136, OCLK[3:0] clock outputs and MCLK
internal clock .
During either a hardware or a software reset, the OCLK[3:0] pins are all logic
low. Immediately following reset, all OCLK[3:0] outputs are active with the output
frequency defined by pll_oclk divided by the initial value in the Table 121, Clock
generator control register (Register_offset 0x10).
X 32 PLL
(400-800 MHz)
MUX
I_DCLK
(80-400 MHz)
4/8/16
E_DCLK
REF_CLK
2/4/6/8
4
O
O
O
O
M
pll_oclk
CK_SEL[1:0]
CK_SEL[3:2]
pll_rclk
I_SCLK_T
I_SCLK_L
(80-400 MHz)
(12.5-25 MHz)
(40-133 MHz)
N
N
N
N
N
6370 drw21
(12.5-25 MHz)
CK_SEL[1:0]
00
01
10
11
CK_SEL[3:2]
00
01
10
11
Function
pll_rclk = REF_CLK
pll_rclk = I_DCLK/16
pll_rclk = I_DCLK /8
pll_rclk = I_DCLK /4
Function
E_DCLK = pll_oclk/2
E_DCLK = pll_oclk/4
E_DCLK = pll_oclk/6
E_DCLK = pll_oclk/8
TABLE 14 – CK_SEL[3:0] INPUT PIN ENCODING
Figure 30. Clock generator
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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