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參數(shù)資料
| 型號(hào)： | IDT88P8344BHGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820 |
| 封裝： | GREEN, PLASTIC, BGA-820 |
| 文件頁數(shù)： | 25/98頁 |
| 文件大?。?/td> | 601K |
| 代理商： | IDT88P8344BHGI |
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IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
4.1 SPI-3 to SPI-4 datapath and flow control
Four packet fragment processor modules fromSPI-3 to SPI-4 are provided.
One packet fragment processor module is associated with one SPI-3 ingress
interface. All four packet fragment processor modules connect to a single SPI-
4 interface.
Packet fragments fromthe SPI-3 ingress are received into the SPI-3 ingress
port buffers. A packet fragment processor transfers complete packet fragments
fromthe SPI-3 ingress port buffers to memory segments previously reserved
on a per-LP basis in the buffer segment pool. The SPI-3 ingress port buffer
watermark and the per-LP free buffer segment threshold information is combined
to produce SPI-3 ingress FIFO status towards the attached device. Packets or
packet fragments received on one SPI-3 ingress logical port can be forwarded
to any one of:
A logical port on the egress SPI-4 interface.
A logical port on an associated SPI-3 interface (between physical port
interfaces A and B, and between C and D only).
The mcroprocessor interface, using the capture buffer.
The connection on the logical port level is performed through an intermediate
mapping to a Link Identification number (LID).
Figure 13. SPI-3 ingress to SPI-4 egress packet fragment processor
6370 drw27
buffer segment pool
PMON & DIAG
SPI3 egress port
buffers
uP
Associated
egress PFP
capture
buffer
SPI-3
redirect
buffers
uP
insert buffer
SPI3 Ingress
SPI4 Egress
FIFO status
FIFO status
SPI3 ingress port
buffers
SPI-3 ingress PFP functions
The packet fragment processor(PFP) receives status information about the
SPI-3 ingress buffers and the mcroprocessor insert buffer. The PFP processes
SPI-3 ingress buffers in high priority and the insert buffer with low priority. The
PFP copies data into the buffer segment , requests new buffer segments, and
generates entries in the SPI4-egress queue.
SPI-3 ingress buffer processing
The PFP verifies whether a SPI-3 ingress buffer is occupied. If the SPI-3
ingress buffer is not occupied the PFP processes the insert buffer.
Normal operation
In loopback mode, all of the SPI-3 ingress buffers of a physical SPI-3 port are
copied into the SP-3 egress buffers of that same port. This is a test mode only,
as no non-loopback traffic can be transferred at this time.
In non – loop back mode (normal operation) the SPI-3 ingress buffers are
forwarded to the LID process by the PFP.
The LID process generates a set of events for an associated LID. The events
that are directed towards the PMON&DIAG module are:
SPI-3 error tagged packet event (errored packets)
SPI-3 EOP event (all packets)
SPI-3 fragment event (all fragments) with an associated length field
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相關(guān)代理商/技術(shù)參數(shù) |
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| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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