參數(shù)資料
型號(hào): IDT88P8344BHGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820
封裝: GREEN, PLASTIC, BGA-820
文件頁(yè)數(shù): 46/98頁(yè)
文件大?。?/td> 601K
代理商: IDT88P8344BHGI
46
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
Indirect Data
(register 0x33)
bit 31…bit 25
Bit 31 is the most significant data bit.
Indirect Data
(register 0x32)
bit 24…bit 16
Indirect Data
(register 0x31)
bit 15…bit 8
Indirect Data
(register 0x30)
bit 7…bit 0
TABLE 18 - BIT ORDER WITHIN A 32-BIT DATA REGISTER
Indirect Data (register 0x30)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 2 bit 0
TABLE 19 - BIT ORDER WITHIN AN 8-BIT DATA REGISTER
Bit 7 is the most significant data bit.
9. REGISTER DESCRIPTION
There are two distinctly different types of register access in the IDT88P8344.
Direct access registers are used for interrupts and other high-priority registers
and for access to the indirect access registers. Direct access registers can be
accessed more quickly than indirect access registers, and are used where this
access speed advantage is required. There are only a limted number of direct
access registers due to the six address lines used on the IDT88P8344. All direct
access registers are one byte wide. Most registers within the IDT88P8344 are
of the indirect access type. Indirect access registers are used for configuration,
maps, etc., that may not need to be accessed as often as the direct registers.
Indirect registers are accessed through special direct access registers designed
for the purpose of allowing indirect access to the large set of registers and maps
that are needed to configure the IDT88P8344.
9.1 Register access summary
The SPI Exchange device uses an indirect addressing scheme for most of
the configuration registers. The indirect registers are accessed through a
protocol where interface pins A[5:0], D[7:0], and control pins are mapped into
internal register space A[15:0], D[31:0], and Control[7:0]. The full
address of
any indirectly addressed register = Module_base + Block_base + Register_offset.
Direct Register Format
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 2 bit 0
Bit 7 is the most significant data bit.
TABLE 17 - BIT ORDER WITHIN AN 8-BIT DATA REGISTER
Figure 34. Direct & indirect access
I
s
C[7:0]
8
6
16
32
6370 drw24
D
s
P
D[7:0]
A[5:0]
C[7:0]
D[31:0]
A[15:0]
9.1.1 Direct register format
All direct register accesses are one byte. The bit ordering for the direct
access registers is shown.
9.1.2 Indirect register format
The internal format for 32 and 8 bit registers is shown below. The registers
are accessed fromthe external processor interface as successive bytes of
indirect data. The indirect register space includes 32-bit data registers and 8-
bit data registers. The directly-addressed register space includes directly-
addressable 8-bit data registers, four 8-bit data registers for indirect data access,
two 8-bit address registers for indirect data access, and an 8-bit control register
for indirect data access.
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