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| 型號： | IDT88P8344BHGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820 |
| 封裝： | GREEN, PLASTIC, BGA-820 |
| 文件頁數(shù)： | 57/98頁 |
| 文件大?。?/td> | 601K |
| 代理商： | IDT88P8344BHGI |
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57
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
TABLE 50 - SPI-3 GENERAL CONFIGURATION
REGISTER (REGISTER_OFFSET=0x00)
Field
Bits
0
1
2
3
4
5
6
7
12:8
31:9
Length
1
1
1
1
1
1
1
1
5
19
Initial Value
0b0
0b1
0b0
0b0
0b0
0b1
0b0
0b0
0x0F
0x000
LINK
PACKET
SPI3_ENABLE
BUSWIDTH
EVEN_PARITY
PARITY_EN
Reserved
Reserved
WATERMARK
Reserved
There is one register for SPI-3 general configuration per SPI-3 interface.
Each register has read and write access. The address for module A is 0x0200,
module B is 0x2200, module C is 0x4200, and module D is 0x6200. The bit fields
of the SPI-3 general configuration register are described in the following
paragraphs.
TABLE 49 - SPI-3 INGRESS LP TO LID MAP
Field
Bits
LID
5:0
ENABLE
6
BIT_REVERSAL
7
Length
6
1
1
Initial Value
0x00
0b0
0b0
There are 256 SPI-3 ingress Logical Port (LP) to Logical Identifier (LID)
registers, one per potential SPI-3 LP. Only 64 LPs per SPI-3 physical interface
can be enabled. An attempt to enable more than 64 LPs per SPI-3 physical
interface or to assign an identical LID to more than one LP will be discarded
and an error code will be returned. The ENABLE bit is used to enable SPI-
3 logical ports. All data fromnon-enabled SPI-logical ports is discarded and
an inactive SPI-3 logical port event is generated. This event is directed towards
the PMON & DIAG module. Disabled ports always generate available status.
The Table 49 - SPI-3 ingress LP to LID Map assigns a LID to a SPI-3 logical
port. LID mapping for 64 out of 256 SPI-3 logical ports is supported on each
SPI-3 physical port. LPs in the SPI Exchange are 8 bits wide[7:0] and range
from0 to 255. An example of mapping SPI-3 physical interface “A”, LP 0x08
to LID 0x05, activating the LID, and not using bit reversal is outlined.
Performan indirect write of 0x45 to register address Module_base 0x0000
+ Block_base 0x0000 + Register_offset 0x08 = 0x0008. Another example of
SPI-3 LP to LID mapping is to map SPI-3 “B”, LP 0xFF to LID 0x3F, write 0x7F
to register Module_base 0x2000 + Block_base 0x0000 + Register_offset
0xFF = 0x20FF.
The Initial Value column is the value of the register after reset.
LID
The LID programmed is associated to the LP with the same
number as the register address. Six bits support the 64 simultaneously active
LIDs per SPI-3 physical interface.
ENABLE
to this LID.
This bit is used to enable or disable the connection of this LP
0=LID disabled
1=LID enabled
BIT_REVERSAL
of the SPI-3 interface on a per-LID basis.
0=Disable bit reversal for this LID
1=Enable bit reversal for this LID
This bit is used to reverse the bit ordering of each byte
9.3.2 Block base 0x0200 registers
SPI-3 general configuration register (Block_base
0x0200 + Register_offset 0x00)
LINK
A SPI-3 interface can be used either in Link or PHY modes. For
connecting to a transmssion line-interface PHY, programthe SPI Exchange for
Link mode. For connecting the SPI-3 interface to an NPU or other Link-mode
device, programthe SPI-3 interface for PHY mode. Note that the four SPI-3
interfaces can be independently configured into either Link or PHY modes. The
SPI-3 ingress and egress of a given SPI-3 physical port will always be in the
same mode.
0= SPI-3 interface in PHY mode
1= SPI-3 interface in Link mode
PACKET
modes. A SPI-3 interface acting as a Link layer device can poll the attached PHY
device for up to 64 LPs if the attached PHY device supports the polling interface.
When attached to a PHY device that only supports byte mode, the four direct
status indicators can be used. Note that the four SPI-3 interfaces can be
independently configured into either BYTE or PACKET modes. When the SPI
Exchange is in PHY mode, the PACKET bit is used to select either a polled or
direct status response to the attached Link device.
0 = BYTE mode with direct status indication for up to 4 LPs [3:0]
1= PACKET mode with polled status for up to 64 LPs
A SPI-3 interface can be used either in BYTE or PACKET
SPI3_ENABLE
A SPI-3 interface can be enabled or disabled according
to the state programmed into this bit. A port should be disabled to save power
if it is not used.
0=SPI-3 Physical port disabled, outputs are in tristate
1=SPI-3 Physical port enabled
BUSWIDTH
bit interface, according to the needs of the attached device. The SPI-3 ingress
and egress of a given SPI-3 physical port will always be of the same bus width.
0=32 bit SPI-3 interface
1=8 bit SPI-3 interface
A SPI-3 interface can be used as either a single 8-bit or 32-
9.3.1 Block base 0x0000 registers
SPI-3 ingress LP to LID map (Block_base 0x0000 +
Register_offset 0x00 to 0xFF)
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| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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