參數(shù)資料
型號(hào)： IDT88P8344BHGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820
封裝： GREEN, PLASTIC, BGA-820
文件頁(yè)數(shù)： 63/98頁(yè)
文件大小： 601K
代理商： IDT88P8344BHGI
63
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
Non critical LID associated capture table
(Block_base 0x0C00 + Register_offset 0x10-0x15)
TABLE 66 - NON CRITICAL LID ASSOCIATED
CAPTURE TABLE (REGISTER_OFFSET 0x10-0x15)
Register
EVENT_TYPE
The Non critical LID associated capture table is at Block_Base 0x0C00 +
Register_Offset 0x10-0x15. The Non critical LID associated capture table is
used to determne the EVENT_TYPE of SPI-3 and SPI-4 per-LID or per-LP
interrupts. The EVENT_TYPE coding is used to indicate which event or events
are pertinent to the interrupt in the Table 64 - LID associated interrupt indication
register(0x0E). The Non critical LID associated capture table is used to
determne the EVENT, and multiple bits can be active at the same time. The Non
critical LID associated capture table is read-only.
SPI-3 to SPI-4 critical LID interrupt indication
registers (Block_base 0x0C00 + Register_offset
0x16-0x17)
TABLE 67 - SPI-3 TO SPI-4 CRITICAL LID INTER-
RUPT INDICATION REGISTERS
(REGISTER_OFFSET 0x16-0x17)
Register
Field
Bits
0x16
LID[31:0]
31:0
0x17
LID[63:32]
31:0
The SPI-3 to SPI-4 critical LID interrupt indication registers are at Block_Base
0x0C00 + Register_offset 0x16-0x17.
Critical events are captured per LID in the SPI-3 to SPI-4 critical LID interrupt
indication registers. An interrupt is generated when enabled by the enable flag
in the SPI-3 to SPI-4 critical LID interrupt enableregisters. A SPI-3 to SPI-4 critical
LID interrupt indication register has read and write access. An interrupt indication
is cleared by writing a logical one to the appropriate bit of a SPI-3 to SPI-4 critical
LID interrupt indication register. Only one kind of critical event is defined-buffer
overflow. Each bit of the LID field set to logical one indicates the presence of a
buffer overflow event. A summary indication of as to which of the two sources,
SPI-3 to SPI-4 or SPI-4 to SPI-3, is responsible for the critical interrupt is indicated
in the Table 71 Critical events source indication register (0x1E).
SPI-3 to SPI-4 critical LID interrupt enable regis-
ters (Block_base 0x0C00 + Register_offset 0x18-
0x19)
TABLE 68 - SPI-3 TO SPI-4 CRITICAL LID INTERRUPT
ENABLE REGISTERS (REGISTER_OFFSET 0x18-
0x19)
Register
Field
Bits
0x18
LID[31:0]
31:0
0x19
LID[63:32]
31:0
The SPI-3 to SPI-4 critical LID interrupt enable registers have read and write
access. A SPI-3 to SPI-4 critical LID interrupt enable register bits enable the
corresponding bits in a SPI-3 to SPI-4 critical LID interrupt indication register.
Associated
field
LP (8 bits)
LID (6 bits)
LID (6 bits)
LID (6 bits)
LID (6 bits)
LID (6 bits)
0x00
0x01
0x02
0x03
0x04
0x05
Inactive ingress SPI-3 logical port event
SPI-3 ingress data parity error
SPI-4 illegal SOP sequence event
SPI-4 illegal EOP sequence event
SPI-3 illegal SOP sequence event
SPI-3 illegal EOP sequence event
Length
32
32
Initial Value
0x00
0x00
Length
32
32
Initial Value
0x00
0x00
SPI-4 to SPI-3 critical LID interrupt indication
registers (Block_base 0x0C00 + Register_offset
0x1A-0x1B)
TABLE 69 - SPI-4 TO SPI-3 CRITICAL LID INTERRUPT
INDICATION REGISTERS (REGISTER_OFFSET
0x1A-0x1B)
Register
Field
Bits
0x1A
LID[31:0]
31:0
0x1B
LID[63:32]
31:0
Length
32
32
Initial Value
0x00
0x00
The SPI-4 to SPI-3 critical LID interrupt indication registers are at Block_Base
0x0C00 + Register_offset 0x1A-0x1B.
Critical events are captured per LID in a SPI-4 to SPI-3 critical LID interrupt
indication register. An interrupt is generated when enabled by the enable flag
in the SPI-4 to SPI-3 critical LID interrupt enableregister. The SPI-4 to SPI-3
critical LID interrupt indication registers have read and write access. An interrupt
indication is cleared by writing a logical one to the appropriate bit of a SPI-4 to
SPI-3 critical LID interrupt indication register. Only one kind of critical event is
defined-buffer overflow. Each bit of a LID field set to logical one indicates the
presence of a buffer overflow event. A summary indication of as to which of the
two sources, SPI-3 to SPI-4 or SPI-4 to SPI-3, is responsible for the critical
interrupt is indicated in the Table 71 Critical events source indication register
(0x1E).
SPI-4 to SPI-3 critical LID interrupt enable regis-
ters (Block_base 0x0C00 + Register_offset 0x1C-
0x1D)
TABLE 70 - SPI-4 TO SPI-3 CRITICAL LID INTER-
RUPT ENABLE REGISTERS (REGISTER_OFFSET
0x1C-0x1D)
Register
Field
Bits
0x1C
LID[31:0]
31:0
0x1D
LID[63:32]
31:0
Length
32
32
Initial Value
0x00
0x00
The SPI-4 to SPI-3 critical LID interrupt enable registers have read and write
access. The SPI-4 to SPI-3 critical LID interrupt enable register bits enable the
corresponding bits in the SPI-4 to SPI-3 critical LID interrupt indication registers.
Critical events source indication register
(Block_base 0x0C00 + Register_offset 0x1E)
TABLE 71 - CRITICAL EVENTS SOURCE INDICA-
TION REGISTER (REGISTER_OFFSET 0x1E)
Field
Bits
SPI34_OVR
0
SPI43_OVR
1
Reserved
31:2
Length
1
1
30
Initial Value
0b0
0b0
0x0
The bits in the Critical events source indication register are read only. Bit
SPI34_OVR reflects the logical OR result of all bits in the SPI-3 to SPI-4 critical
LID associated interrupt indication registers. Bit SPI43_OVR reflects the logical
OR result of all bits in the SPI-4 to SPI-3 critical LID interrupt indication registers.
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