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參數(shù)資料
| 型號： | IDT88P8344BHGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820 |
| 封裝： | GREEN, PLASTIC, BGA-820 |
| 文件頁數(shù)： | 70/98頁 |
| 文件大?。?/td> | 601K |
| 代理商： | IDT88P8344BHGI |
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70
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
SPI-4_EN
The SPI-4 ingress path is enabled using this field. The SPI-4
path is disabled during reset and while configuring the port, and then is enabled
for normal use.
0=SPI-4 ingress is disabled
1= SPI-4 ingress is enabled
I_CLK_EDGE
is selected using the I_CLK_EDGE field.
0=SPI-4 ingress LVTTL status clock uses the rising edge
1= SPI-4 ingress LVTTL status clock uses the falling edge
The SPI-4 ingress LVTTL status clock active clock edge
I_DSC
during de-skew.
The I_DSC bit is used to protect against a randomdata error
0= One de-skew result is needed for data de-skew
1= Two consecutive de-skew results are needed for data de-skew
(recommended setting)
I_INSYNC_THR
is controlled using the I_INSYNC_THR field. It is recommended to use the initial
value.
The SPI-4 ingress DIP-4 in synchronization threshold
I_OUTSYNC_THR
The SPI-4 ingress DIP-4 out-of synchronization
threshold is controlled using the I_OUTSYNC_THR field. It is recommended to
use the initial value.
I_CSW_EN
The ingress calendar switch enable bit is used to enable the
switching of the active calendars. It is recommended to use the initial value.
0=Ingress calendar switch disabled. Only SPI-4 ingress calendar_0
is used.
1=Ingress calendar switch enabled. Calendar_0 or calendar_1 can
be used.
CAL_SEL
calendar_0 and SPI-4 ingress calendar_1. The CAL_SEL bit is only valid if the
I_CSW_EN bit is set to a logic one.
0=SPI-4 ingress calendar_0 is selected
1=SPI-4 ingress calendar_1 is selected if the I_CSW_EN bit is set to
a logic one
The calendar select bit selects between SPI-4 ingress
I_LOW
The I_LOW field selects the SPI-4 ingress clock frequency range.
0=SPI-4 ingress clock is greater than or equal to 200 MHz
1=SPI-4 ingress clock is less than 200 MHz
SPI-4 ingress status configuration register
(Block_base 0x0300 + Register_offset 0x01)
FIFO_MAX_T
interval between scheduling of training sequences on the FIFO status path
interface. The units are the number of times the calendar is sent before
scheduling the training sequence.
The SPI-4 ingress FIFO_MAX_T field is the maximumtime
ALPHA_FIFO
repetitions of the status training sequence that must be scheduled every
FIFO_MAX_T cycles. The value for alpha used is actually one more than the
ALPHA_FIFO value programmed into the ALPHA_FIFO field.
The SPI-4 ingress ALPHA_FIFO field is the number of
SPI-4 ingress status register (Block_base 0x0300 +
Register_offset 0x02)
TABLE 91 - SPI-4 INGRESS STATUS REGISTER
(REGISTER_OFFSET 0x02)
Field
Bits
I_SYNCH
0
I_DSK_OOR
1
DCLK_AV
2
TABLE 90 - SPI-4 INGRESS STATUS CONFIGURA-
TION REGISTER (REGISTER_OFFSET 0x01)
Field
Bits
FIFO_MAX_T
23:0
ALPHA_FIFO
31:24
Length
24
8
Initial Value
0
0
The SPI-4 ingress status configuration register is at Block_base 0x0300 and
has read and write access.
The SPI-4 ingress status configuration register is used to set the state of the
SPI-4 ingress FIFO status path interface. The bit fields of the SPI-4 ingress status
configuration register are described.
Length
1
1
1
Initial Value
0
0
0
The SPI-4 ingress status register is at Block_base 0x0300 and has read-only
access.
The SPI-4 ingress status register is used to set the state of the SPI-4 ingress
synchronization.
The bit fields of the SPI-4 ingress status register are described.
I_SYNCH
The SPI-4 ingress I_SYNCH field describes the synchroniza-
tion state of the SPI-4 ingress data path.
0=SPI-4 ingress data path is out of synchronization
1=SPI-4 ingress data path is in synchronization
I_DSK_OOR
The SPI-4 ingress I_DSK_OOR field describes the de-skew
state of the SPI-4 ingress data path.
0=SPI-4 ingress data path de-skew is within range
1= SPI-4 ingress data path de-skew is out of range
DCLK_AV
state of the SPI-4 ingress clock.
0=SPI-4 ingress clock is not available
1= SPI-4 ingress clock is available
The SPI-4 ingress DCLK_AV field describes the availability
SPI-4 ingress inactive transfer port (Block_base
0x0300 + Register_offset 0x03)
TABLE 92 - SPI-4 INGRESS INACTIVE TRANSFER
PORT (REGISTER_OFFSET 0x03)
Field
Bits
INACT_LP
7:0
Length
8
Initial Value
0
The SPI-4 ingress inactive transfer port is at Block_base 0x0300 and has
read-only access.
The SPI-4 ingress inactive transfer port INACT_LP field is used to monitor
the LP associated with the latest inactive transfer. The INACT_LP field can
change at any time and is used for diagnostics only.
INACT_LP
of the LP associated with the last inactive LP transfer, used for diagnostics only.
The SPI-4 ingress INACT_LP field contains the numeric value
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| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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