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參數(shù)資料
| 型號： | IDT88P8344BHGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820 |
| 封裝： | GREEN, PLASTIC, BGA-820 |
| 文件頁數(shù)： | 31/98頁 |
| 文件大?。?/td> | 601K |
| 代理商： | IDT88P8344BHGI |
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IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
SPI-4 ingress interface configurable parameters:
The IDT88P8344 can interface to either a Link or a PHY layer device. The
SPI-4 port can be enabled or disabled.
The SPI-4 ingress bits are aligned with the ingress clock. In addition, the SPI-
4 words are then aligned among each other to produce valid words. This is
performed both on the data channel and the status channel. The bit alignment
algorithmruns as long as the interface is active. The word alignment algorithm
is run during training intervals.
SPI-4 ingress per-LID configurable parameters
SPI-4 to SPI-3 LID map
256 entries, one per SPI-4 LP
SPI-3 physical interface identifier
SPI-3 LID
Enable bit per LID
SPI-4 ngress packet ength check
Each LID on the SPI-4 ingress interface has the ability to be programmed for
mnimumand maximumpacket length. The mnimumpacket length can be set
from0 to 255 bytes in one byte increments. The maximumpacket length can
be set from0 to 16,383 bytes in one byte increments. Packets shorter or longer
than set by these parameters will be optionally counted in the short or long packet
counter for that LID.
SPI-3 egress configurable parameters
Length of SPI-3 packet fragment
All packet fragments froma particular SPI-3 physical interface are program-
mable to an equal length with the possible exception of an EOP fragment which
may be shorter.
SPI-3 egress poll length
Applies when the SPI-3 interface is acting as a Link layer device when using
the packet level polling mode
Causes polling of the PHY for the logical ports associated with LIDs ranging
from[0 up to POLL_LENGTH] to find logical ports that can accept data
Poll range is 0-63 LPs.
SPI-3 egress per-LID configurable parameters
Many parameters to control the flow of data are programmable per LID. The
following paragraphs describe these parameters.
SPI-3 egress LID to LP map
one map per SPI-3 physical port
64 entries per map, one per LID
LP enable bit per LP
Bit reversal enable per LP
SPI-3 egress multiple burst enable
Multiple Burst Enable allows more than one burst to be sent to an LP. This
feature is included to relieve systems with long latency between updates. When
this feature is not enabled, only one burst per LP is allowed into the round robin
SPI-3 egress buffers at a time.
SPI-4 ingress to SPI-3 egress data memory
SPI-3 egress control
There is a SPI-3 egress port descriptor table for the paths out of the data
memory. The function a SPI-3 egress port descriptor table is to define where
data goes after leaving the main data memory. There are three configurable
options:
SPI-3 egress
Mcroprocessor Interface Capture
Discard
Maximum number of memory segments
Defines the largest Buffer available to an LP / LID
Each segment is 256 bytes
Range 1 – 508 in increments of one segment
The figure below shows the datapath through the device fromthe SPI-4
interface to the SPI-3 interface.
Figure 19. SPI-4 ingress to SPI-3 egress datapath
…
…
JTAG
uproc
LID Counters Memory
4 x SPI-3
8 bit / 32 bit
Min: 19.44MHz
Max: 133MHz
I
Chip Counters Memory
I
SPI-3 /
LID map
Main
Memory
A
SPI-4.2
Min: 80 MHz
Max:400 MHz
SPI-4 /
LID map
6370 drw13
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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