6-26
Video Interface and On-Screen Display
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
locations immediately following the OSD header, and outputs it synchro-
nously to the display controller. Regions that are not covered by OSD
data show the underlying video picture. When the OSD controller outputs
the last line of the OSD region, it immediately loads the next 128 bits
from the display list and the process repeats itself. Note that the OSD
controller never needs to load the OSD registers while OSD data is dis-
played. This means that the OSD registers can be single buffered. Only
one OSD region is active at a time.
The OSD can be operated in two modes: Linked List Mode and No
6.9.3
OSD Control
Registers
The OSD controller automatically loads the OSD control registers as
troller.” The OSD control registers are not accessible from the micropro-
cessor interface. The OSD controller loads the OSD control registers
through the DRAM Data Registers (Group 7, Registers 5 through 12)
from the attached DRAM as two 64-bit loads.
Figure 6.14 illustrates the
organization of an OSD le with 4 bits-per-pixel resolution. This gure
indicates the order in which the bytes need to be written to the DRAM.
The LSB of the header, bits [7:0], are written through Group 7, Index 5.
The next most signicant byte, bits [15:8], are written through Group 7,
Index 6, and so on, until all the bytes are written. Similarly, all the corre-
sponding bits in the color palette and bitmap data need to be written
through appropriate indices of the Group 7 DRAM Data Registers.