L64005 MPEG-2 Audio/Video Decoder Technical Manual
1-19
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
1.5.5
PES Decoding
The L64005 is capable of decoding either separate video and audio
streams, or a program stream (PES) containing both audio and video
streams.
1.5.6
Video Output
The L64005 provides a digitized video output for subsequent display.
This data is in the CCIR 601 (Y, Cb, Cr) color space. The video output
operates with a luminance sample rate that is always exactly half the
device clock—nominally 13.5 MHz from a 27-MHz clock. The L64005
provides video synchronization signals in master mode, or can accept
external synchronization signals in slave mode.
1.5.7
Audio Output
The audio decoder produces a serial PCM, or I2S output that is compat-
ible with most commercial audio DACs. Since the audio and video decod-
ers operate off the same clock, synchronization is greatly simplied. The
audio decoder includes circuitry to maintain the correct audio output
sample rate regardless of the input clock rate.
1.5.8
User Interface
A user port allows you to program system options and monitor the oper-
ation of the device. Errors agged by the L64005 and user data present
in this channel may be read through this port. However, the device will
not maintain unread user data indenitely. Once the L64005 FIFO is full,
no more data is written to the FIFO and subsequent data will be lost. The
system controller must read data transmitted in the user data records of
the MPEG bitstream, even if that data is subsequently used to control
some aspect of the video display subsystem. To avoid losing data, the
controller must read this data, then write it to L64005 internal state reg-
isters, if necessary. The user port is also used to write data into the video
overlay memory.
1.5.9
Memory
Utilization
The L64005 supports direct connection to regular or synchronous
DRAMs for use as frame stores, channel buffers, and overlay memory.
The L64005 uses frame stores for intermediate frame reconstruction and
display, separate video and audio channel buffers for rate matching, and
zero or more regions for graphical overlay. This storage is combined into
a single contiguous memory space accessed over a 64-bit wide bus. In
most cases this will be four 256k x 16 regular DRAMs, or a single
1M x 16 SDRAM, for a total memory space of 2 MByte. The interface
between the L64005 and external memory requires no external compo-