L64005 MPEG-2 Audio/Video Decoder Technical Manual
2-19
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
Note that once the FIFO has overrun, the status bits stay
at 112 until the register is read. The L64005 will then
mark the FIFO as full until a subsequent read clears the
full condition or it once again becomes overrun.
The following paragraphs describe the function of bits [5:0] during a write
only.
R
Reserved
[7:6], W
These bits are reserved.
RE
Reset Channel and PES Buffer on Error
5, W
Setting RE causes the decoder to reset the channel buff-
ers and the PES buffer if the system parser detects an
error in the system stream. If RE is cleared, the decoder
will not reset the buffers on error.
VSS
Video Stream Select Enable
4, W
Setting VSS causes the decoder to check the ID of the
video stream before decoding it. Clearing VSS causes
the decoder to decode all video streams.
VIDEOID
Video Stream ID
[3:0], W
VIDEOID is used to select the stream ID of the audio
stream to be decoded when VSS is set.
2.5
Group 3
Interrupt
Register 0
The Group 3 Interrupt Register 0 contains a number of interrupt status
bits and masks. Reading the register clears all pending interrupts in this
register. Clearing these bits enables the corresponding interrupt; setting
these bits disables the corresponding interrupts. An interrupt is only gen-
erated if there are no pending interrupts for that bit. After an interrupt is
generated, each subsequent interrupt event related to that bit is ignored
until the initial interrupt is cleared. All bits in this register are read/write.
UDFS[1:0]
User Data FIFO Status
002
Empty
012
Data is ready
102
Full (additional writes will
cause FIFO to overrun)
112
Overrun