L64005 MPEG-2 Audio/Video Decoder Technical Manual
5-19
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
The anchor frame areas store I and P frames only. The B frame area
implements a circular buffer for B frame data. This buffer is one frame
long for interlaced systems. The system controller can write to the VBI
data, and the display controller can display the VBI data area during the
vertical blanking interval. To alternate between more than one VBI data
area, redirect the VBI data pointer in real time. Different pointers access
chroma and luma data in each of the data areas. The L64005 stores data
in an identical format in the anchor frame, B frame, and VBI data areas
to simplify the display controller and the macroblock access logic.
5.4.1
Luma Frame
Organization
A distance equal to the pitch of the display separates consecutive lines
of luminance data. For example, if the reconstructed image is 720 pixels
wide, then each line of luminance occupies 720 bytes, or 90 DRAM
words.
5.4.2
Chroma Frame
Organization
The L64005 interleaves chroma pixels (Cr, Cb, Cr, Cb) within the same
64-bit word to increase the word fetch efciency of the DRAM interface.
5.4.3
Random
Read/Write to
Frame Store
The user may read and write to the frame store through the user inter-
face port. Accessing the frame store through the interface is primarily
intended for system test. It is also intended for writing data into the part
of the frame store reserved for display during vertical blanking interval.
ing reading and writing the frame store. Reads or writes required for
image decoding or display always preempt reads or writes requested by
the user.
5.5
Channel Buffer
Architecture
The L64005 interfaces to 2 Mbytes of external memory (DRAMs) through
the External DRAM interface bus, BD[63:0]. This memory space stores
compressed MPEG data, reconstructed frames of images, and on-screen
display data. The memory space that stores compressed MPEG data is
referred to as the channel buffers. The user denes the channel buffers
and programs the space allocation through the L64005 registers. The
channel buffer space is divided into four separate channel buffer sec-
tions. The user programs the L64005 registers to dene each of these
four channel buffer section spaces, as shown in
Table 5.5.