L64005 MPEG-2 Audio/Video Decoder Technical Manual
3-9
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
TESTCLK
Synchronous DRAM Test Clock
Input
TESTCLK is used to provide a test clock to the L64005
when its internal PLL is bypassed by tying BYPASS to a
logic ‘0’.
BYPASS
PLL Bypass
Input
BYPASS, when pulled to a logic ‘0’, causes the L64005’s
internal PLL to be bypassed and TESTCLK to become an
input to be used for providing the 81 MHz clock to the
device. This pin must be pulled up to Vdd through a resis-
tor for proper operation when using the on-chip PLL. A
value of 4.7K ohms is recommended for the resistor.
3.4
Video Interface
The video interface consists of all the required signals to control an exter-
nal display device.
Figure 3.4 illustrates the timing relationships for the
signals in the video interface
BLANK
Blank
Output
BLANK is a composite blank output from the L64005 dis-
play controller. Its polarity is user dened.
CREF
Chroma Reference
Output
CREF is the output signal that indicates when the Cb
component is currently on the PD bus. When CREF is
asserted HIGH it indicates that Cb data is on PD[7:0].
When CREF is deasserted LOW, it indicates that either
Y or Cr data is on PD[7:0]. The order of the Cr and Cb
components can be changed by proper programming of
Register 31 in Group 7.
HS
Horizontal Sync
Bidirectional
In slave mode, HS is used to reset the horizontal
counters in the display controller. The horizontal sync sig-
nal should be synchronous to SYSCLK. In master mode
the display controller programs the HS timing. The polar-
ity is user dened. HS can also be programmed to act as
a composite sync output by proper programming of Reg-
ister 31 in Register Group 7.
PD[7:0]
Pixel Data Output Bus
Output
The data on the PD[7:0] bus represents the pixel data of
the reconstructed picture. The pixel data is formatted in
CCIR601 YCbCr chromanicity.