L64005 MPEG-2 Audio/Video Decoder Technical Manual
2-47
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
When the 11/12 time or 13/12 time has been played for
one frame, the audio decoder resets these bits to 012
(normal) to let the user know that the frame has been
completed. In these modes, the audio decoder presents
11/12 of the normal data to the output PCM lter (fast) or
13/12 of the normal data to the output PCM lter (slow)
within 1 normal frame decode. Reset these bits to 002 to
enable pause mode. Note that in the pause mode, the
audio decoder stops parsing the bitstream and maintains
all current states, so that re-asserting normal play at a
later time does not cause the audio decoder to lose sync
with the bitstream.
2.8.34
Group 6
Reserved
Registers
Registers 55 through 63 are reserved for LSI Logic use and should not
be read or written.
2.9
Group 7
Secondary
Control
Registers
The Group 7 Secondary Control Registers access secondary control
functions inside the L64005. These registers may be accessed indirectly
through the Address Indirection Register. Most of the registers need to
be set only once during initialization of the decoder.
2.9.1
Group 7
Auxiliary Data
FIFO
When read, Register 0 returns the value on the top of the Auxiliary Data
FIFO and pops the FIFO. Reading the FIFO when empty yields an unde-
ned value. Failing to read the FIFO will eventually result in loss of data
from the FIFO, but will produce no other errors in the decoding process.
Writing the register has no effect.
AUXFIFO
Auxiliary Data FIFO
[7:0], R
This eight-bit register is used to access auxiliary data in
the coded data stream. The FIFO is 128 bytes deep for
revisions C and later of the device. The FIFO is 80 bytes
deep in revisions A and B.
Table 2.4 shows the available parameters, their arrival order, and their
size. All values are right justied within their corresponding bytes in the
FIFO.