L64005 MPEG-2 Audio/Video Decoder Technical Manual
2-21
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
more information.
DFR
Data FIFO Ready
1, R/W
When DFR is set, it indicates that there is data in the
user data FIFO or the auxiliary data FIFO. Read the user
data FIFO status or the auxiliary data FIFO status to
determine the state.
DES
Decode Status
0, R/W
When DES is set, it indicates the video decoder is run-
ning. When DES is clear, it indicates that the decoder has
stopped. Setting DES starts the decoder. Clearing DES
stops the decoder.
2.6
Group 4
Interrupt
Register 1
The Group 4 Interrupt Register 1 contains a number of interrupt status
bits and masks. Reading the register clears all pending interrupts in this
register. Clearing these bits enables the corresponding interrupts; setting
these bits disables the corresponding interrupts. All bits in this register
are read/write.
Figure 2.5
Group 4 Interrupt
Register 1
VPR
Video PES Data Ready
7, R/W
When set, VPR indicates that the system parser has just
written a PES header into the video system buffer.
APR
Audio PES Data Ready
6, R/W
When set, APR indicates that the system parser has just
written a PES header into the audio system buffer.
BVB
Begin Vertical Blank
5, R/W
When set, BVB indicates that the vertical blanking inter-
val has begun. If enabled, this interrupt occurs once per
eld.
BAV
Begin Active Video
4, R/W
When set, BAV indicates that the active video portion of
a eld is being displayed. If enabled, this interrupt occurs
once per eld.
7
6
5
43210
VPR APR BVB BAV VCU ACU VCO ACO