4-10
Video Data Flow
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
best to blank the screen during this type of skip because the picture
becomes greatly disrupted.
4.3
Channel Buffer
Operation
The Channel Buffers store incoming channel data using memory that is
attached to the L64005. The device implements a unied buffer, in which
the channel buffers and frame stores use the same memory space. The
device has up to four buffers active at one time. The four buffers are
listed below.
Video Elementary Stream Data Buffer
Audio Elementary Stream Data Buffer
Video PES Packet Header Buffer
Audio PES Packet Header Buffer
When operating with an MPEG-1 system stream or an MPEG-2 program
stream, the decoder sends all system data to the Audio PES Packet
Header Buffer, and the Video PES Packet Header Buffer is unused. See
4.3.1
Channel Buffer
Hardware
The channel buffers are implemented using available space in external
DRAM memory. The available size of the buffers depends on the resolu-
tion of the frame and the set of features invoked in the display controller.
In CCIR601 NTSC resolution systems, the total available DRAM space
for channel buffers is about 4 Mbits, which supports channel rates up to
16 Mbits/s. In CCIR601 PAL, the larger picture size reduces the total
available DRAM space for channel buffers to about 1.875 Mbits. This
meets the MPEG-2 recommended size in the Main Prole at Main Level.
If the amount of buffer memory is insufcient, the buffers can extend off
the chip using the VREQ or AREQ handshake signals, and can be con-
tinued, for example, in another memory attached to an MPEG Transport
Layer chip. Users should ensure that some portion of the buffer still
resides on the L64005 so that the decoder does not get starved of data.
The minimum buffering requirement specied by MPEG-2 “main level,
main prole” is approximately 1.8 Mbits. See
Chapter 5 for more informa-
tion on the physical Channel Buffer Interface.
Each channel buffer size may be specied in increments of 256 bytes
using user programmable channel buffer start and end address registers.