L64005 MPEG-2 Audio/Video Decoder Technical Manual
2-35
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
2.8.20
Group 6
Display
Controller
Status
The bits in Register 31 indicate the current eld status of the display con-
troller.
VCD
VCode Delay
[7:4], R/W
This eld is used to program the number of line delays
from the end of Main_Lines until the VCode is set to ‘1’.
This eld is normally set to 0x0 such that the VCode
turns on at the start of Post_Blank_Lines. However, if a
non-zero value is programmed into this eld, there will be
a delay until the VCode shows up in the SAV and EAV
word. This delay is equal to VCode_Delay + I lines where
I=0 in even elds and I=1 in odd elds when
VCode_Delay is not equal to zero.
ODFF
Odd Field First
3, R
This bit indicates whether an odd eld is coded before an
even eld in the MPEG video stream. The L64005 sets
ODFF either when the rst eld of a single frame is an
odd eld, or when the rst eld of a three eld pulldown
sequence is an odd eld.
Figure 2.7 shows an example
of ODFF bit setting during normal operation. This bit is
initially synchronized to top=odd=rst and reects
whether the display controller is in the rst or last eld of
a frame. When performing a pulldown, the rst two elds
are considered to be the rst eld.
LAF
Last Active Field
2, R
This bit may be used to determine whether the last dis-
played eld of a picture was an odd or an even eld. The
L64005 sets LAF while displaying either the last eld of
a single frame, or the last eld of a three eld pulldown
sequence.
Figure 2.7 shows an example of LAF bit set-
ting during normal operation.
7
4
3
210
VCD
ODFF LAF BTF EOF
Register 31