L64005 MPEG-2 Audio/Video Decoder Technical Manual
2-63
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
2.9.26
Group 7
DRAM Source
Address
Registers
Registers 48 through 50 store the 18-bit DRAM address of the data block
to be transferred in a block move operation. The address stored in this
register can be written directly or will be auto-incremented (for the next
cycle) if DRAM block move is enabled. The normal DRAM address is
used as the destination address for a block move. These registers are
read/write.
2.9.27
Group 7
DRAM Transfer
Count Registers
Registers 51 and 52 stores the DRAM transfer word count. Each time
that a block move DRAM read and write cycle completes, the L64005
decrements the value of the DRAM transfer word count and generates
an interrupt when the count reaches zero. This count is also used to
count the number of DMA transfers that are made into DRAM from the
external VREQ and VVALID lines.
2.9.28
Group 7
DRAM Transfer
Mode Register
Two bits of this register, DRAM_MODE[1:0] dene the type of transfer
mode the DRAM controller executes. The parity resets to “002” – Host
Access DRAM.
R
Reserved
[7:3]
These bits are reserved.
FLUSH
Flush DRAM FIFO
2
Setting FLUSH clears the internal DRAM FIFO and
returns the DRAM interface to the ready state. After the
host performs a burst of reads, this operation is neces-
sary before the host can perform a burst of writes.
DRAM_MODE[1:0]
DRAM Transfer Mode
[1:0], R/W
These bits dene the type of transfer mode that the
DRAM controller executes.
72
1
0
R
FLUSH
DRAM_MODE[1:0]
Register 53