L64005 MPEG-2 Audio/Video Decoder Technical Manual
6-17
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
6.5.1.2 Vertical Timing
Vertical timing parameters are measured in half-line or full-line times,
using the half-line parameter dened in the horizontal timing. The user
must write to the control registers over the L64005 user interface to set
these parameters.
Table 6.9
Vertical Timing
of Common TV
Systems
1. H = Horizontal Line Time
6.5.2
VCode Delay
For those applications where a digital monitor is connected directly to the
video output (rather than a TV via a multi-standard encoder), the L64005
can be programmed to give the correct timings for Rec. 656 line number
positioning for Vcode changes in NTSC and Master mode. Group 6, Reg-
ister 31, bits [7:4] is the V Code Delay (VCD) register and is used to pro-
gram the number of line delays from the end of Main_Lines until the
VCode is set to a ‘1’. Refer to Section 2.8.20. This is not needed for PAL
because the number of Main_Lines is the same for both even and odd
elds, but for NTSC each eld has a different number of Main_Lines
(243/244). This register is normally set to 0x0 so that the VCode turns
on at the start of Post_Blank_Lines. The delay is equal to VCD + x lines,
where x = 0 in even elds (with even number of lines) and x = 1 for the
odd elds (with odd number of lines). For example, if VCD is pro-
grammed with 0x3 it will result in the even eld VCode turning on in the
third line of post-blank and the odd eld VCode turning on in the fourth
line of post-blank.
6.5.3
Slave Mode
In slave mode, the L64005 synchronizes to an external synchronization
master. Note that in this case, the display timing registers in the L64005
still need to be programmed as outlined in the previous sections. How-
Parameter
NTSC-M
PAL
(I,G,B)
Unit
Pre-equalization
3
2.5
H1
Serration
3
2.5
H
Post-equalization
3
2.5
H
Vertical Blank
21
25
H
Number of Lines/Field
262.5
312.5
H
Scan Lines/Field
253
305
H