Timers (Timer B)
123
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Timer B
Figure 1.15.1 shows a block diagram of the timer B. Figures 1.15.2 and 1.15.3 show registers related to the
timer B.
Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits of TBiMR register (i = 0 to 5)
to select the desired mode.
Timer mode: The timer counts an internal count source.
Event counter mode: The timer counts pulses from an external device or overflows or underflows of
other timers.
Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
Figure 1.15.1. Timer B Block Diagram
Timer Bi mode register (i=0 to 5)
Symbol
Address
After reset
00XX0000
2
00XX0000
2
TB0MR to TB2MR
TB3MR to TB5MR
039B
16
to 039D
16
035B
16
to 035D
16
Bit name
Function
Bit symbol
TMOD0
RW
b7
b6
b5
b4
b3
b2
b1
b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period measurement mode,
pulse width measurement mode
1 1 : Must not be set
TCK1
MR3
MR2
MR1
TMOD1
MR0
TCK0
Function varies with each operation
mode
Count source select bit
Operation mode select bit
(Note 1)
(Note 2)
RO
Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.
RW
RW
RW
RW
RW
RW
RW
Function varies with each operation
mode
Clock source selection
Event counter
Timer
Pulse period measuremnet,
pulse width measurement
Reload register
Low-order 8 bits
High-order 8 bits
Data bus low-order bits
Data bus high-order bits
f
1
or f
2
f
8
f
32
f
C32
TBj overflow (Note)
(j = i – 1. Note, however,
j = 2 when i = 0,
j = 5 when i = 3)
Can be selected in only
event counter mode
TABSR register
TBSR register
Polarity switching
and edge pulse
TBi
IN
(i = 0 to 5)
Counter reset circuit
Counter
TBi Address
Timer B0 0391
16
0390
16
Timer B1 0393
16
0392
16
Timer B2 0395
16
0394
16
Timer B1
Timer B3 0351
16
0350
16
Timer B4 0353
16
0352
16
Timer B5 0355
16
0354
16
Timer B4
TBj
Timer B2
Timer B0
Timer B5
Timer B3
Clock selection
Note: Overflow or underflow.
Figure 1.15.2. TB0MR to TB5MR Registers