
Timers (Timer B)
124
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Symbol
TABSR
Address
0380
16
After reset
00
16
Count start flag
TA0S
b7
b6
b5
b4
b3
b2
b1
b0
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
Timer B1 count start flag
TB1S
Timer B2 count start flag
Timer A4 count start flag
Timer A3 count start flag
Timer A1 count start flag
Timer A0 count start flag
1 : Starts counting
TB2S
TA4S
TA3S
TA1S
Symbol
CPSRF
Address
0381
16
After reset
0XXXXXXX
2
Clock prescaler reset flag
Bit name
Function
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
(When read, the value of this bit is “0”.)
Clock prescaler reset flag
CPSR
Symbol
TB0
TB1
TB2
TB3
TB4
TB5
Address
0391
16
, 0390
16
0393
16
, 0392
16
0395
16
, 0394
16
0351
16
, 0350
16
0353
16
, 0352
16
0355
16
, 0354
16
After reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
b7
b0 b7
b0
(b15)
(b8)
Timer Bi register (i=0 to 5)(Note 1)
RW
Measures a pulse period or width
Function
Symbol
TBSR
Address
0340
16
After reset
000XXXXX
2
Timer B3, B4, B5 count start flag
Bit name
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
Timer B4 count start flag
TB4S
AAAAAAAAAAAAAAA
contents are indeterminate.
(b4-b0)
Timer B5 count start flag
1 : Starts counting
TB5S
Function
Nothing is assigned. When write, set to “0”. When read, their
RW
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
(b6-b0)
Note 1: The register must be accessed in 16 bit units.
Note 2: The timer counts pulses from an external device or overflows or underflows of other timers.
Divide the count source by n + 1
where n = set value
Timer mode
Event counter
mode
Pulse period
modulation mode,
Pulse width
modulation mode
0000
16
to FFFF
16
Divide the count source by n + 1
where n = set value (Note 2)
0000
16
to FFFF
16
Setting this bit to “1” initializes the
Mode
Setting range
Figure 1.15.3. TB0 to TB5 Registers, TABSR Register, TBSR Register, CPSRF Register