Serial I/O (Special Modes)
168
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Detection of Start and Stop Condtion
Whether a start or a stop condition has been detected is determined.
A start condition-detected interrupt request is generated when the SDAi pin changes state from high to
low while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated
when the SDAi pin changes state from low to high while the SCLi pin is in the high state.
Because the start and stop condition-detected interrupts share the interrupt control register and vec-
tor, check the UiSMR register’s BBS bit to determine which interrupt source is requesting the interrupt.
Figure 1.20.3. Detection of Start and Stop Condition
Output of Start and Stop Condition
A start condition is generated by setting the UiSMR4 register (i = 0 to 2)’s STAREQ bit to “1” (start).
A restart condition is generated by setting the UiSMR4 register’s RSTAREQ bit to “1” (start).
A stop condition is generated by setting the UiSMR4 register’s STPREQ bit to “1” (start).
A start condition is output by setting the STAREQ bit to “1” and then the UiSMR4 register’s STSPSEL
bit to “1” (start). Similarly, a restart condition is output by setting the RSTAREQ bit to “1” and then the
STSPSEL bit to “1”, and a stop condition is output by setting the STPREQ bit to “1” and then the
STSPSEL bit to “1”.
Table 1.20.5 and Figure 1.20.4 show the functions of the STSPSEL.
If start, stop and restart conditions are to be output, make sure no interrupts will occur between the
instruction that sets the STAREQ, STPREQ or RSTAREQ bit to “1” and the instruction that sets the
STSPSEL bit to “1”.
Also, if a start condition is to be output, make sure the STAREQ bit is set to “1” before setting the
STSPSEL bit to “1”.
3 to 6 cycles < duration for setting-up (Note)
3 to 6 cycles < duration for holding (Note)
i = 0 to 2
Note: When the PCLKR register's PCLK1 bit = 1, this is the cycle number of
f
1SIO
, and the PCLK1 bit = 0, this is the cycle number of f
2SIO
.
Duration for
setting up
Duration for
holding
SCLi
SDAi
(Start condition)
SDA i
(Stop condition)