185
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
SI/O3, SI/O4
SI/Oi bit rate generator (i = 3, 4) (Notes 1, 2)
b7
b0
Symbol
S3BRG
S4BRG
Address
0363
16
0367
16
After
reset
Indeterminate
Indeterminate
Description
Assuming that set value = n, BRGi divides the count
source by n + 1
00
16
to FF
16
Setting range
RW
SI/Oi transmit/receive register (i = 3, 4) (Note 1, 2)
b7
b0
Symbol
S3TRR
S4TRR
Address
0360
16
0364
16
After
reset
Indeterminate
Indeterminate
Description
Transmission/reception starts by writing transmit data to this register. After
transmission/reception finishes, reception data can be read by reading this register.
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: To receive data, set the corresponding port direction bit for S
IN
i to “0” (input mode).
S I/Oi control register (i = 3, 4) (Note 1)
Symbol
S3C
S4C
Address
0362
16
0366
16
After reset
0100000
16
0100000
16
b7
b6
b5
b4
b3 b2
b1
b0
Description
SMi5
SMi1
SMi0
SMi3
SMi6
SMi7
Internal synchronous
clock select bit
Transfer direction select
bit
Synchronous clock
select bit
S I/Oi port select bit
S
OUT
i initial value
set bit
1SIO
or f
2SIO
0 1 : Selecting f
8SIO
1 0 : Selecting f
32SIO
1 1 : Must not be set.
0 : S
OUT
i output
1 : S
OUT
i output disable
(high impedance)
b1 b0
0 : External clock
1 : Internal clock
Effective when SMi3 = 0
0 : “L” output
1 : “H” output
0 : Input/output port
1 : S
OUT
i output, CLKi function
Bit name
Bit
symbol
0 : LSB first
1 : MSB first
SMi2
S
OUT
i output disable bit
Note 1: Make sure this register is written to by the next instruction after setting the PRCR register's PRC2 bit to “1”
(write enable).
Note 2: Set the SMi3 bit to “1” (S
OUT
i output, CLKi function).
Note 3: Set the SMi3 bit to “1” and the corresponding port direction bit to “0” (input mode).
Note 4: Effective when SMi3 bit = 1.
CLK polarity select bit
SMi4
0 : Transmit data is output at falling edge of
transfer clock and receive data is input at
rising edge
1 : Transmit data is output at rising edge of
transfer clock and receive data is input at
falling edge
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
RW
RW
(Note 4)
(Note 2)
(Note 3)
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: Use MOV instruction to write to this register.
Figure 1.21.2.
S3C and S4C Registers, S3BRG and S4BRG Registers, and S3TRR and S4TRR Registers