Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O (Clock Synchronous Serial I/O)
148
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Clock Synchronous serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.18.1
lists the specifications of the clock synchronous serial I/O mode. Table 1.18.2 lists the registers used in
clock synchronous serial I/O mode and the register values set.
Item
Specification
Transfer data format
Transfer clock
Transfer data length: 8 bits
UiMR(i=0 to 2) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f
1SIO
, f
2SIO
, f
8SIO
, f
32SIO
. n: Setting value of UiBRG register 00
16
to FF
16
CKDIR bit = “1” (external clock) : Input from CLKi pin
Selectable from CTS function, RTS function or CTS/RTS function disable
Before transmission can start, the following requirements must be met (Note 1)
_
The TE bit of UiC1 register= 1 (transmission enabled)
_
The TI bit of UiC1 register = 0 (data present in UiTB register)
_
If CTS function is selected, input on the CTSi pin = “L”
Before reception can start, the following requirements must be met (Note 1)
_
The RE bit of UiC1 register= 1 (reception enabled)
_
The TE bit of UiC1 register= 1 (transmission enabled)
_
The TI bit of UiC1 register= 0 (data present in the UiTB register)
For transmission, one of the following conditions can be selected
_
The UiIRS bit (Note 3) = 0 (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
_
The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
CLK polarity selection
Transfer data input/output can be chosen to occur synchronously with the rising or
the falling edge of the transfer clock
LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
Continuous receive mode selection
Reception is enabled immediately by reading the UiRB register
Switching serial data logic
This function reverses the logic value of the transmit/receive data
Transfer clock output from multiple pins selection (UART1)
The output pin can be selected in a program from two UART1 transfer clock pins that
have been set
Separate CTS/RTS pins (UART0)
CTS
0
and RTS
0
are input/output from separate pins
Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit = “0”
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit data output at the rising edge
and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
Note 2:
If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.
Note 3:
The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
Transmission, reception control
Transmission start condition
Reception start condition
Error detection
Select function
Interrupt request
generation timing
Table 1.18.1. Clock Synchronous Serial I/O Mode Specifications