
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generation Circuit
54
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
System clock control register 1 (Note 1)
Symbol
CM1
Address
0007
16
After reset
00100000
2
Bit
Function
Bit symbol
b7
b6
b5
b4
0
b3
0
b2
0
b1
b0
CM10
All clock stop control bit
(Notes 4, 6)
System clock select bit 1
(Notes 6, 7)
0 : Clock on
1 : All clocks off (stop mode)
Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Note 2: When entering stop mode from high or middle speed mode, or when the CM05 bit is set to “1” (main clock turned off) in low
speed mode, the CM15 bit is set to “1” (drive capability high).
Note 3: Effective when the CM06 bit is “0” (CM16 and CM17 bits enable).
Note 4: If the CM10 bit is “1” (stop mode), X
OUT
goes “H” and the internal feedback resistor is disconnected. The X
CIN
and X
COUT
pins are placed in the high-impedance state. When the CM11 bit is set to “1” (PLL clock), or the CM20 bit of CM2 register is
set to “1” (oscillation stop, re-oscillation detection function enabled), do not set the CM10 bit to “1”.
Note 5: After setting the PLC07 bit in PLC0 register to “1” (PLL operation), wait until Tsu (PLL) elapses before setting the CM11 bit to
“1” (PLL clock).
Note 6: When the PM21 bit of PM2 register is set to “1” (clock modification disable), writing to the CM10, CM011 bits has no effect.
When the PM22 bit of PM2 register is set to “1” (watchdog timer count source is ring oscillator clock), writing to the CM10 bit
has no effect.
Note 7: Effective when CM07 bit is “0” and CM21 bit is “0” .
CM15
X
IN
-X
OUT
drive capacity
select bit (Note 2)
0 : LOW
1 : HIGH
RW
CM16
CM17
Reserved bit
Must set to
“0”
Main clock division
select bit 1 (Note 3)
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
b7 b6
CM11
0 : Main clock
1 : PLL clock (Note 5)
RW
RW
RW
RW
RW
RW
(b4-b2)
Figure 1.9.3. CM1 Register