294
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Differences Between M16C/62P and M16C/62A
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Item
M16C/62A
M16C/62P
Serial I/O
(UART0 to UART2)
(UART, clock synchronous,) x 2
(UART, clock synchronous, IIC bus, IE bus)
x 1
Selectable: f
1
, f
8
, f
32
(UART, clock synchronous, I
2
C bus, IE bus)
x 3
Differences in Mask ROM version and Flash memory version (2) (Note)
Timers A, B count
source
Timer A two-phase
pulse signal
processing
Selectable: f
1
, f
8
, f
32
, f
C32
Selectable: f
1
, f
2
, f
8
, f
32
, f
C32
Timer functions for
three-phase motor
control
No Z-phase (counter reset input
Z-phase (counter reset) input is available
No function protect by protect register
Count source is selectable:
f
1,
f
f
32,
f
C32
Dead time timer count source is fixed at f
1
/2
Function protect by protect register
Count source is selectable:
f
1,
f
2,
f
8,
f
32,
f
C32
Dead time timer count source is selectable:
f
1,
f
1
divided by 2, f
2
, f
2
divided by 2
Output polarity is selectable
Carrier wave phase detectable
Three-phase output port NMI control
UART0 to UART2,
SI/O3, SI/O4 count
source
Selectable: f
1SIO
, f
2SIO
, f
8SIO
, f
32SIO
Serial I/O sleep
function
Serial I/O I
2
C mode
A-D converter
SI/O3, SI/O4 clock
polarity selection
10 bits X 8 channels
Expandable up to 10 channels
Selectable
Have
Analog or digital delay is selected as SDA
delay
SDA digital delay count source: 1/ f(X
IN
)
Serial I/O I
2
C mode
SDA delay
Not selectable
None
10 bits X 8 channels
Expandable up to 26 channels
Only digital delay is selected as SDA delay
SDA digital delay count source: BRG
Note: About the details and the electric characteristics, refer to data sheet.
UART2 data transmit
timing
After data was written, transfer starts at the
2nd BRG overflow timing
(same as UART0 and UART1)
After data was written, transfer starts at the
1st BRG overflow timing
(Output starts one cycle of BRG overflow
earlier than UART0 and UART1)
Start condition, stop condition:
Auto-generationable
Start condition, stop condition:
Not auto-generationable
A-D converter
operation clock
Selectable: f
AD
, f
AD
/2, f
AD
/4
Selectable: f
AD
, f
AD
divided by 2, 3, 4, 6, 12
A-D converter
input pin
Fixed at port P10
Selectable: ports P0, P2, P10
Assert low when receive buffer is read
Assert low when reception is completed
Serial I/O RTS timing
CTS/RTS separate
function
None
Have