參數(shù)資料
型號(hào)： M68HC16Y1CFC
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, MICROCONTROLLER, PQFP16
封裝： QFP-160
文件頁數(shù)： 21/138頁
文件大?。?/td> 784K
代理商： M68HC16Y1CFC
MC68HC16Y1
MOTOROLA
MC68HC16Y1TS/D
117
The MRM can also operate in a special emulator mode that simplifies emulation of the array by an ex-
ternal device. Emulation mode is enabled by the EMUL bit in the MRMCR. EMUL state is determined
by the state of the DATA10 and DATA13 lines during reset. If both data lines are held low, EMUL is set,
and ROM emulation mode is enabled.
While emulation mode is enabled, the internal module chip select signal (CSM) is asserted whenever a
valid access to an address assigned to the masked ROM module is made. To be valid, an access must
be within the range specified by the ROM base array registers and must meet the address space re-
quirements defined by the ASPC field in MRMCR. CSM is asserted for all valid read accesses; it is as-
serted for write accesses only in background debug mode. The MRM does not acknowledge an access
on the IMB while in emulation mode — this causes the SCIM to run an external bus cycle. The CSM
signal is asserted on the falling edge of AS. Internal DSACK is generated by the ROM module after it
has inserted the number of wait states specified by the WAIT field in the MRMCR.
9.1 Masked ROM Control Registers
The 32-byte control register block contains registers that are used to configure the MRM and to control
ROM array function. Configuration information is specified and programmed at the same time as the
ROM content.
*Reset state of STOP = DATA14. Reset state of EMUL = (DATA10
DATA13).
STOP — Stop Bit
0 = Normal ROM operation
1 = Disable ROM and activate emulator mode if enabled
Reset state of STOP is the complement of DATA14 state during reset. ROM array base address cannot
be changed unless STOP is set.
BOOT — Boot ROM Control Bit
0 = CPU16 accesses ROM array addresses after reset
1 = CPU16 cannot access ROM array addresses after reset
Reset state of BOOT is specified by the user. Bootstrap function is overridden if STOP = 1.
LOCK — Lock Registers Bit
0 = Write lock disabled; protected registers and fields can be written
1 = Write lock enabled; protected registers and fields cannot be written
Reset state of LOCK is specified by the user. LOCK protects the ASPC and WAIT fields, as well as the
ROMBAL and ROMBAH registers. ASPC, ROMBAL and ROMBAH are also protected by the STOP bit.
EMUL — Emulator Mode Control Bit
0 = Normal ROM operation
1 = MRM enters emulator mode when STOP is set.
Reset state of EMUL is the complement of DATA10 and DATA13 state during reset. When EMUL is set,
the MRM responds to accesses by asserting the CSM signal.
MRMCR — Masked ROM Module Configuration Register
$YFF820
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STOP
0
BOOT
LOCK
EMUL
ASPC
WAIT
0
RESET:
*
0
USER
SPEC
USER
SPEC
*
USER
SPEC
USER
SPEC
0
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