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參數(shù)資料
| 型號： | M68HC16Y1CFC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP16 |
| 封裝： | QFP-160 |
| 文件頁數(shù)： | 9/138頁 |
| 文件大?。?/td> | 784K |
| 代理商： | M68HC16Y1CFC |
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MOTOROLA
MC68HC16Y1
106
MC68HC16Y1TS/D
SIZE — Transfer Data Size
0 = 8-bit data transfer
1 = 16-bit data transfer
BAUD — Serial Clock Baud Rate
The SPI uses a modulus counter to derive SCK baud rate from the MCU system clock. Baud rate is
selected by writing a value from 2 to 255 into the BR field. Giving BR a value of zero or one disables
the baud rate generator. The following equations determine the SCK baud rate:
SCK Baud Rate = System Clock/(2
BR)
or
BR = System Clock/(2
SCK Baud Rate Desired)
SPSR contains SPI status information. Only the SPI can set the bits in this register. The CPU reads the
register to obtain status information and writes it to clear status flags.
SPIF — SPI Finished Flag
0 = SPI not finished
1 = SPI finished
WCOL — Write Collision
0 = No write collision occurred
1 = Write collision occurred
MODF — Mode Fault Flag
0 = Normal operation
1 = Another SPI node requested to become the network SPI master while the SPI was enabled in
master mode (SS input taken low).
A write to SPDR initiates transmission or reception in the master device. At the completion of transmis-
sion, the SPIF status bit is set in both master and slave devices. Received data is buffered. SPIF must
be cleared before a subsequent transfer of data from the shift register to the buffer or overrun occurs
— the byte or word that causes overrun is lost. Transmitted data is not buffered — a write to SPDR plac-
es data directly into the shift register for transmission.
UPPB — Upper Byte
In 16-bit transfer mode, UPPB is used to access the most significant 8 bits of the data. Bit 15 of the
SPDR is the MSB of the 16-bit data.
LOWB — Lower Byte
In 8-bit transfer mode, data is accessed at the address of LOWB. MSB in 8-bit transfer mode is bit 7 of
the SPDR. In 16-bit transfer mode, LOWB holds the least significant 8 bits of the data.
SPSR — SPI Status Register
$YFFC3C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPIF
WCOL
0
MODF
0
RESET:
0
SPDR — SPI Data Register
$YFFC3E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UPPB
LOWB
RESET:
U
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